389 lines
12 KiB
C
389 lines
12 KiB
C
/* $NetBSD: siop_pci_common.c,v 1.34 2010/11/13 13:52:08 uebayasi Exp $ */
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/*
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* Copyright (c) 2000 Manuel Bouyer.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* SYM53c8xx PCI-SCSI I/O Processors driver: PCI front-end */
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: siop_pci_common.c,v 1.34 2010/11/13 13:52:08 uebayasi Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <sys/buf.h>
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#include <sys/kernel.h>
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#include <machine/endian.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsipiconf.h>
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#include <dev/ic/siopreg.h>
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#include <dev/ic/siopvar_common.h>
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#include <dev/pci/siop_pci_common.h>
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/* List (array, really :) of chips we know how to handle */
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static const struct siop_product_desc siop_products[] = {
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{ PCI_PRODUCT_SYMBIOS_810,
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0x00,
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"Symbios Logic 53c810 (fast scsi)",
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SF_PCI_RL | SF_CHIP_LS,
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4, 8, 3, 250, 0
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},
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{ PCI_PRODUCT_SYMBIOS_810,
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0x10,
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"Symbios Logic 53c810a (fast scsi)",
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SF_PCI_RL | SF_PCI_BOF | SF_CHIP_PF | SF_CHIP_LS,
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4, 8, 3, 250, 0
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},
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{ PCI_PRODUCT_SYMBIOS_815,
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0x00,
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"Symbios Logic 53c815 (fast scsi)",
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SF_PCI_RL | SF_PCI_BOF,
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4, 8, 3, 250, 0
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},
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{ PCI_PRODUCT_SYMBIOS_820,
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0x00,
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"Symbios Logic 53c820 (fast wide scsi)",
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SF_PCI_RL | SF_CHIP_LS | SF_BUS_WIDE,
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4, 8, 3, 250, 0
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},
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{ PCI_PRODUCT_SYMBIOS_825,
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0x00,
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"Symbios Logic 53c825 (fast wide scsi)",
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SF_PCI_RL | SF_PCI_BOF | SF_BUS_WIDE,
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4, 8, 3, 250, 0
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},
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{ PCI_PRODUCT_SYMBIOS_825,
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0x10,
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"Symbios Logic 53c825a (fast wide scsi)",
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SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
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SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS |
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SF_BUS_WIDE,
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7, 8, 3, 250, 4096
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},
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{ PCI_PRODUCT_SYMBIOS_860,
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0x00,
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"Symbios Logic 53c860 (ultra scsi)",
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SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
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SF_CHIP_PF | SF_CHIP_LS |
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SF_BUS_ULTRA,
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4, 8, 5, 125, 0
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},
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{ PCI_PRODUCT_SYMBIOS_875,
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0x00,
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"Symbios Logic 53c875 (ultra-wide scsi)",
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SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
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SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS |
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SF_BUS_ULTRA | SF_BUS_WIDE,
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7, 16, 5, 125, 4096
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},
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{ PCI_PRODUCT_SYMBIOS_875,
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0x02,
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"Symbios Logic 53c875 (ultra-wide scsi)",
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SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
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SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR |
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SF_CHIP_LS | SF_CHIP_10REGS |
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SF_BUS_ULTRA | SF_BUS_WIDE,
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7, 16, 5, 125, 4096
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},
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{ PCI_PRODUCT_SYMBIOS_875J,
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0x00,
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"Symbios Logic 53c875j (ultra-wide scsi)",
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SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
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SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR |
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SF_CHIP_LS | SF_CHIP_10REGS |
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SF_BUS_ULTRA | SF_BUS_WIDE,
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7, 16, 5, 125, 4096
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},
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{ PCI_PRODUCT_SYMBIOS_885,
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0x00,
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"Symbios Logic 53c885 (ultra-wide scsi)",
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SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
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SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR |
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SF_CHIP_LS | SF_CHIP_10REGS |
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SF_BUS_ULTRA | SF_BUS_WIDE,
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7, 16, 5, 125, 4096
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},
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{ PCI_PRODUCT_SYMBIOS_895,
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0x00,
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"Symbios Logic 53c895 (ultra2-wide scsi)",
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SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
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SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
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SF_CHIP_LS | SF_CHIP_10REGS |
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SF_BUS_ULTRA2 | SF_BUS_WIDE,
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7, 31, 7, 62, 4096
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},
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{ PCI_PRODUCT_SYMBIOS_896,
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0x00,
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"Symbios Logic 53c896 (ultra2-wide scsi)",
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SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
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SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
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SF_CHIP_LS | SF_CHIP_10REGS |
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SF_BUS_ULTRA2 | SF_BUS_WIDE,
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7, 31, 7, 62, 8192
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},
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{ PCI_PRODUCT_SYMBIOS_895A,
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0x00,
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"Symbios Logic 53c895a (ultra2-wide scsi)",
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SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
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SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
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SF_CHIP_LS | SF_CHIP_10REGS |
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SF_BUS_ULTRA2 | SF_BUS_WIDE,
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7, 31, 7, 62, 8192
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},
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{ PCI_PRODUCT_SYMBIOS_1010,
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0x00,
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"Symbios Logic 53c1010-33 rev 0 (ultra3-wide scsi)",
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SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
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SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM |
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SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR |
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SF_CHIP_GEBUG |
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SF_BUS_ULTRA3 | SF_BUS_WIDE,
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7, 31, 0, 62, 8192
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},
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{ PCI_PRODUCT_SYMBIOS_1010,
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0x01,
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"Symbios Logic 53c1010-33 (ultra3-wide scsi)",
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SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
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SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM |
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SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR | SF_CHIP_DT |
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SF_CHIP_GEBUG |
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SF_BUS_ULTRA3 | SF_BUS_WIDE,
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7, 62, 0, 62, 8192
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},
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{ PCI_PRODUCT_SYMBIOS_1010_2,
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0x00,
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"Symbios Logic 53c1010-66 (ultra3-wide scsi)",
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SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
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SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM |
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SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR | SF_CHIP_DT |
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SF_CHIP_AAIP |
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SF_BUS_ULTRA3 | SF_BUS_WIDE,
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7, 62, 0, 62, 8192
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},
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{ PCI_PRODUCT_SYMBIOS_1510D,
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0x00,
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"Symbios Logic 53c1510d (ultra2-wide scsi)",
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SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
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SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
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SF_CHIP_LS | SF_CHIP_10REGS |
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SF_BUS_ULTRA2 | SF_BUS_WIDE,
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7, 31, 7, 62, 4096
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},
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{ 0,
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0x00,
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NULL,
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0x00,
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0, 0, 0, 0, 0
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},
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};
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const struct siop_product_desc *
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siop_lookup_product(uint32_t id, int rev)
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{
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const struct siop_product_desc *pp;
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const struct siop_product_desc *rp = NULL;
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if (PCI_VENDOR(id) != PCI_VENDOR_SYMBIOS)
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return NULL;
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for (pp = siop_products; pp->name != NULL; pp++) {
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if (PCI_PRODUCT(id) == pp->product && pp->revision <= rev)
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if (rp == NULL || pp->revision > rp->revision)
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rp = pp;
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}
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return rp;
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}
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int
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siop_pci_attach_common(struct siop_pci_common_softc *pci_sc,
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struct siop_common_softc *siop_sc, struct pci_attach_args *pa,
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int (*intr)(void *))
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{
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pci_chipset_tag_t pc = pa->pa_pc;
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pcitag_t tag = pa->pa_tag;
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const char *intrstr;
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pci_intr_handle_t intrhandle;
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bus_space_tag_t iot, memt;
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bus_space_handle_t ioh, memh;
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pcireg_t memtype;
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prop_dictionary_t dict;
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int memh_valid, ioh_valid;
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bus_addr_t ioaddr, memaddr;
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bool use_pciclock;
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aprint_naive(": SCSI controller\n");
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pci_sc->sc_pp =
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siop_lookup_product(pa->pa_id, PCI_REVISION(pa->pa_class));
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if (pci_sc->sc_pp == NULL) {
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aprint_error("sym: broken match/attach!!\n");
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return 0;
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}
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/* copy interesting infos about the chip */
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siop_sc->features = pci_sc->sc_pp->features;
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#ifdef SIOP_SYMLED /* XXX Should be a devprop! */
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siop_sc->features |= SF_CHIP_LED0;
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#endif
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dict = device_properties(siop_sc->sc_dev);
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if (prop_dictionary_get_bool(dict, "use_pciclock", &use_pciclock))
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if (use_pciclock)
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siop_sc->features |= SF_CHIP_USEPCIC;
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siop_sc->maxburst = pci_sc->sc_pp->maxburst;
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siop_sc->maxoff = pci_sc->sc_pp->maxoff;
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siop_sc->clock_div = pci_sc->sc_pp->clock_div;
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siop_sc->clock_period = pci_sc->sc_pp->clock_period;
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siop_sc->ram_size = pci_sc->sc_pp->ram_size;
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siop_sc->sc_reset = siop_pci_reset;
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aprint_normal(": %s\n", pci_sc->sc_pp->name);
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pci_sc->sc_pc = pc;
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pci_sc->sc_tag = tag;
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siop_sc->sc_dmat = pa->pa_dmat;
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memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 0x14);
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switch (memtype) {
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case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
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case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
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memh_valid = (pci_mapreg_map(pa, 0x14, memtype, 0,
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&memt, &memh, &memaddr, NULL) == 0);
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break;
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default:
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memh_valid = 0;
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}
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ioh_valid = (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0,
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&iot, &ioh, &ioaddr, NULL) == 0);
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if (memh_valid) {
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siop_sc->sc_rt = memt;
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siop_sc->sc_rh = memh;
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siop_sc->sc_raddr = memaddr;
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} else if (ioh_valid) {
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siop_sc->sc_rt = iot;
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siop_sc->sc_rh = ioh;
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siop_sc->sc_raddr = ioaddr;
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} else {
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aprint_error_dev(siop_sc->sc_dev,
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"unable to map device registers\n");
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return 0;
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}
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if (siop_sc->features & SF_CHIP_RAM) {
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int bar;
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switch (memtype) {
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case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
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bar = 0x18;
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break;
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case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
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bar = 0x1c;
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break;
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default:
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aprint_error_dev(siop_sc->sc_dev,
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"invalid memory type %d\n",
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memtype);
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return 0;
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}
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if (pci_mapreg_map(pa, bar, memtype, 0,
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&siop_sc->sc_ramt, &siop_sc->sc_ramh,
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&siop_sc->sc_scriptaddr, NULL) == 0) {
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aprint_normal_dev(siop_sc->sc_dev,
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"using on-board RAM\n");
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} else {
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aprint_error_dev(siop_sc->sc_dev,
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"can't map on-board RAM\n");
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siop_sc->features &= ~SF_CHIP_RAM;
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}
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}
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if (pci_intr_map(pa, &intrhandle) != 0) {
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aprint_error_dev(siop_sc->sc_dev, "couldn't map interrupt\n");
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return 0;
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}
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intrstr = pci_intr_string(pa->pa_pc, intrhandle);
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pci_sc->sc_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO,
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intr, siop_sc);
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if (pci_sc->sc_ih != NULL) {
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aprint_normal_dev(siop_sc->sc_dev, "interrupting at %s\n",
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intrstr ? intrstr : "unknown interrupt");
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} else {
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aprint_error_dev(siop_sc->sc_dev,
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"couldn't establish interrupt");
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if (intrstr != NULL)
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aprint_error(" at %s", intrstr);
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aprint_error("\n");
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return 0;
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}
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pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
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pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) |
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PCI_COMMAND_MASTER_ENABLE);
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return 1;
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}
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void
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siop_pci_reset(struct siop_common_softc *sc)
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{
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int dmode;
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dmode = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE);
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if (sc->features & SF_PCI_RL)
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dmode |= DMODE_ERL;
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if (sc->features & SF_PCI_RM)
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dmode |= DMODE_ERMP;
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if (sc->features & SF_PCI_BOF)
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dmode |= DMODE_BOF;
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if (sc->features & SF_PCI_CLS)
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bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL,
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bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL) |
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DCNTL_CLSE);
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if (sc->features & SF_PCI_WRI)
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bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3,
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bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) |
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CTEST3_WRIE);
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if (sc->maxburst) {
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int ctest5 = bus_space_read_1(sc->sc_rt, sc->sc_rh,
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SIOP_CTEST5);
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bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4,
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bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) &
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~CTEST4_BDIS);
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dmode &= ~DMODE_BL_MASK;
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dmode |= ((sc->maxburst - 1) << DMODE_BL_SHIFT) & DMODE_BL_MASK;
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ctest5 &= ~CTEST5_BBCK;
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ctest5 |= (sc->maxburst - 1) & CTEST5_BBCK;
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bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, ctest5);
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} else {
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bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4,
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bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) |
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CTEST4_BDIS);
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}
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bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE, dmode);
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}
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