57 lines
2.4 KiB
C
57 lines
2.4 KiB
C
/* $NetBSD: pca9564reg.h,v 1.1 2010/04/09 10:09:50 nonaka Exp $ */
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/*
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* Copyright (c) 2010 NONAKA Kimihiro <nonaka@netbsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_IC_PCA9564REG_H_
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#define _DEV_IC_PCA9564REG_H_
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#define PCA9564_I2CSTA 0x00 /* R: Status */
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#define PCA9564_I2CCTO 0x00 /* W: Time-out */
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#define PCA9564_I2CDAT 0x01 /* R/W: Data */
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#define PCA9564_I2CADR 0x02 /* R/W: Own address */
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#define PCA9564_I2CCON 0x03 /* R/W: Control */
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/* Control */
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#define I2CCON_CR0 (1 << 0) /* Clock Rate Bit0 */
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#define I2CCON_CR1 (1 << 1) /* Clock Rate Bit1 */
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#define I2CCON_CR2 (1 << 2) /* Clock Rate Bit2 */
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#define I2CCON_CR_330KHZ (0x0)
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#define I2CCON_CR_288KHZ (0x1)
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#define I2CCON_CR_217KHZ (0x2)
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#define I2CCON_CR_146KHZ (0x3)
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#define I2CCON_CR_88KHZ (0x4)
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#define I2CCON_CR_59KHZ (0x5)
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#define I2CCON_CR_44KHZ (0x6)
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#define I2CCON_CR_36KHZ (0x7)
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#define I2CCON_CR_MASK (0x7)
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#define I2CCON_SI (1 << 3) /* Serial Interrupt Flag */
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#define I2CCON_STO (1 << 4) /* Stop Flag */
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#define I2CCON_STA (1 << 5) /* Start Flag */
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#define I2CCON_ENSIO (1 << 6) /* SIO Enable Bit */
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#define I2CCON_AA (1 << 7) /* Assert Acknowledge Flag */
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#endif /* _DEV_IC_PCA9564REG_H_ */
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