344 lines
9.9 KiB
C
344 lines
9.9 KiB
C
/* $NetBSD: txcsbus.c,v 1.13 2002/10/02 05:26:51 thorpej Exp $ */
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/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by UCHIYAMA Yasushi.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <machine/intr.h>
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#include <machine/bus.h>
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#include <machine/bus_space_hpcmips.h>
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#include <machine/platid.h>
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#include <machine/platid_mask.h>
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#include <hpcmips/tx/tx39var.h>
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#include <hpcmips/tx/txcsbusvar.h>
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#include <hpcmips/tx/tx39biuvar.h>
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#include <hpcmips/tx/tx39biureg.h>
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#include "locators.h"
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/* TX39 CS mapping. (nonconfigurationable) */
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const struct csmap {
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char *cs_name;
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paddr_t cs_addr;
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psize_t cs_size;
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} __csmap[] = {
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[TX39_CS0] = {"CS0(ROM)" , TX39_SYSADDR_CS0 ,
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TX39_SYSADDR_CS_SIZE},
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[TX39_CS1] = {"CS1" , TX39_SYSADDR_CS1 ,
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TX39_SYSADDR_CS_SIZE},
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[TX39_CS2] = {"CS2" , TX39_SYSADDR_CS2 ,
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TX39_SYSADDR_CS_SIZE},
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[TX39_CS3] = {"CS3" , TX39_SYSADDR_CS3 ,
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TX39_SYSADDR_CS_SIZE},
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[TX39_MCS0] = {"MCS0" , TX39_SYSADDR_MCS0 ,
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TX39_SYSADDR_MCS_SIZE},
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[TX39_MCS1] = {"MCS1" , TX39_SYSADDR_MCS1 ,
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TX39_SYSADDR_MCS_SIZE},
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#ifdef TX391X
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[TX39_MCS2] = {"MCS2" , TX39_SYSADDR_MCS2 ,
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TX39_SYSADDR_MCS_SIZE},
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[TX39_MCS3] = {"MCS3" , TX39_SYSADDR_MCS3 ,
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TX39_SYSADDR_MCS_SIZE},
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#endif /* TX391X */
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[TX39_CARD1] = {"CARD1(io/attr)", TX39_SYSADDR_CARD1 ,
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TX39_SYSADDR_CARD_SIZE},
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[TX39_CARD2] = {"CARD2(io/attr)", TX39_SYSADDR_CARD2 ,
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TX39_SYSADDR_CARD_SIZE},
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[TX39_CARD1MEM] = {"CARD1(mem)" , TX39_SYSADDR_CARD1MEM ,
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TX39_SYSADDR_CARD_SIZE},
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[TX39_CARD2MEM] = {"CARD2(mem)" , TX39_SYSADDR_CARD2MEM ,
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TX39_SYSADDR_CARD_SIZE},
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};
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int txcsbus_match(struct device *, struct cfdata *, void *);
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void txcsbus_attach(struct device *, struct device *, void *);
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int txcsbus_print(void *, const char *);
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int txcsbus_search(struct device *, struct cfdata *, void *);
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struct txcsbus_softc {
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struct device sc_dev;
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tx_chipset_tag_t sc_tc;
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/* chip select space tag */
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struct bus_space_tag_hpcmips *sc_cst[TX39_MAXCS];
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};
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CFATTACH_DECL(txcsbus, sizeof(struct txcsbus_softc),
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txcsbus_match, txcsbus_attach, NULL, NULL);
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static bus_space_tag_t __txcsbus_alloc_cstag(struct txcsbus_softc *,
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struct cs_handle *);
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int
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txcsbus_match(struct device *parent, struct cfdata *cf, void *aux)
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{
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struct csbus_attach_args *cba = aux;
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platid_mask_t mask;
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if (strcmp(cba->cba_busname, cf->cf_name))
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return (0);
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if (cf->cf_loc[TXCSBUSIFCF_PLATFORM] == TXCSBUSIFCF_PLATFORM_DEFAULT)
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return (1);
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mask = PLATID_DEREF(cf->cf_loc[TXCSBUSIFCF_PLATFORM]);
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if (platid_match(&platid, &mask))
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return (2);
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return (0);
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}
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void
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txcsbus_attach(struct device *parent, struct device *self, void *aux)
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{
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struct csbus_attach_args *cba = aux;
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struct txcsbus_softc *sc = (void*)self;
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sc->sc_tc = cba->cba_tc;
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printf("\n");
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/*
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* Attach external chip.
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*/
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config_search(txcsbus_search, self, txcsbus_print);
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}
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int
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txcsbus_print(void *aux, const char *pnp)
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{
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#define PRINTIRQ(i) i, (i) / 32, (i) % 32
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struct cs_attach_args *ca = aux;
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if (ca->ca_csreg.cs != TXCSBUSCF_REGCS_DEFAULT) {
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printf(" regcs %s %dbit %#x+%#x",
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__csmap[ca->ca_csreg.cs].cs_name,
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ca->ca_csreg.cswidth,
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ca->ca_csreg.csbase,
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ca->ca_csreg.cssize);
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}
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if (ca->ca_csio.cs != TXCSBUSCF_IOCS_DEFAULT) {
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printf(" iocs %s %dbit %#x+%#x",
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__csmap[ca->ca_csio.cs].cs_name,
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ca->ca_csio.cswidth,
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ca->ca_csio.csbase,
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ca->ca_csio.cssize);
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}
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if (ca->ca_csmem.cs != TXCSBUSCF_MEMCS_DEFAULT) {
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printf(" memcs %s %dbit %#x+%#x",
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__csmap[ca->ca_csmem.cs].cs_name,
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ca->ca_csmem.cswidth,
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ca->ca_csmem.csbase,
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ca->ca_csmem.cssize);
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}
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if (ca->ca_irq1 != TXCSBUSCF_IRQ1_DEFAULT) {
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printf(" irq1 %d(%d:%d)", PRINTIRQ(ca->ca_irq1));
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}
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if (ca->ca_irq2 != TXCSBUSCF_IRQ2_DEFAULT) {
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printf(" irq2 %d(%d:%d)", PRINTIRQ(ca->ca_irq2));
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}
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if (ca->ca_irq3 != TXCSBUSCF_IRQ3_DEFAULT) {
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printf(" irq3 %d(%d:%d)", PRINTIRQ(ca->ca_irq3));
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}
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return (UNCONF);
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}
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int
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txcsbus_search(struct device *parent, struct cfdata *cf, void *aux)
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{
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struct txcsbus_softc *sc = (void*)parent;
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struct cs_attach_args ca;
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ca.ca_tc = sc->sc_tc;
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ca.ca_csreg.cs = cf->cf_loc[TXCSBUSCF_REGCS];
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ca.ca_csreg.csbase = cf->cf_loc[TXCSBUSCF_REGCSBASE];
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ca.ca_csreg.cssize = cf->cf_loc[TXCSBUSCF_REGCSSIZE];
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ca.ca_csreg.cswidth = cf->cf_loc[TXCSBUSCF_REGCSWIDTH];
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if (ca.ca_csreg.cs != TXCSBUSCF_REGCS_DEFAULT) {
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ca.ca_csreg.cstag = __txcsbus_alloc_cstag(sc, &ca.ca_csreg);
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}
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ca.ca_csio.cs = cf->cf_loc[TXCSBUSCF_IOCS];
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ca.ca_csio.csbase = cf->cf_loc[TXCSBUSCF_IOCSBASE];
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ca.ca_csio.cssize = cf->cf_loc[TXCSBUSCF_IOCSSIZE];
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ca.ca_csio.cswidth = cf->cf_loc[TXCSBUSCF_IOCSWIDTH];
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if (ca.ca_csio.cs != TXCSBUSCF_IOCS_DEFAULT) {
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ca.ca_csio.cstag = __txcsbus_alloc_cstag(sc, &ca.ca_csio);
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}
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ca.ca_csmem.cs = cf->cf_loc[TXCSBUSCF_MEMCS];
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ca.ca_csmem.csbase = cf->cf_loc[TXCSBUSCF_MEMCSBASE];
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ca.ca_csmem.cssize = cf->cf_loc[TXCSBUSCF_MEMCSSIZE];
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ca.ca_csmem.cswidth = cf->cf_loc[TXCSBUSCF_MEMCSWIDTH];
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if (ca.ca_csmem.cs != TXCSBUSCF_MEMCS_DEFAULT) {
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ca.ca_csmem.cstag = __txcsbus_alloc_cstag(sc, &ca.ca_csmem);
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}
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ca.ca_irq1 = cf->cf_loc[TXCSBUSCF_IRQ1];
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ca.ca_irq2 = cf->cf_loc[TXCSBUSCF_IRQ2];
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ca.ca_irq3 = cf->cf_loc[TXCSBUSCF_IRQ3];
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if (config_match(parent, cf, &ca)) {
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config_attach(parent, cf, &ca, txcsbus_print);
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}
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return (0);
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}
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bus_space_tag_t
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__txcsbus_alloc_cstag(struct txcsbus_softc *sc, struct cs_handle *csh)
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{
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tx_chipset_tag_t tc = sc->sc_tc;
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int cs = csh->cs;
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int width = csh->cswidth;
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struct bus_space_tag_hpcmips *iot;
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txreg_t reg;
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if (!TX39_ISCS(cs) && !TX39_ISMCS(cs) && !TX39_ISCARD(cs)) {
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panic("txcsbus_alloc_tag: bogus chip select %d", cs);
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}
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/* Already setuped chip select */
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if (sc->sc_cst[cs]) {
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return (&sc->sc_cst[cs]->bst);
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}
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iot = hpcmips_alloc_bus_space_tag();
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hpcmips_init_bus_space(iot, hpcmips_system_bus_space_hpcmips(),
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__csmap[cs].cs_name, __csmap[cs].cs_addr, __csmap[cs].cs_size);
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sc->sc_cst[cs] = iot;
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/* CS bus-width (configurationable) */
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switch (width) {
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default:
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panic("txcsbus_alloc_tag: bogus bus width %d", width);
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case 32:
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if (TX39_ISCS(cs)) {
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reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG);
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reg |= (1 << cs);
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tx_conf_write(tc, TX39_MEMCONFIG0_REG, reg);
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} else if(TX39_ISMCS(cs)) {
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#ifdef TX391X
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panic("txcsbus_alloc_tag: MCS is 16bit only");
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#endif /* TX391X */
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#ifdef TX392X
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reg = tx_conf_read(tc, TX39_MEMCONFIG1_REG);
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reg |= ((cs == TX39_MCS0) ?
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TX39_MEMCONFIG1_MCS0_32 :
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TX39_MEMCONFIG1_MCS1_32);
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tx_conf_write(tc, TX39_MEMCONFIG1_REG, reg);
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#endif /* TX392X */
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}
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break;
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case 16:
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if (TX39_ISCS(cs)) {
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reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG);
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reg &= ~(1 << cs);
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tx_conf_write(tc, TX39_MEMCONFIG0_REG, reg);
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} else if(TX39_ISMCS(cs)) {
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/* TX391X always 16bit port */
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#ifdef TX392X
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reg = tx_conf_read(tc, TX39_MEMCONFIG1_REG);
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reg &= ~((cs == TX39_MCS0) ?
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TX39_MEMCONFIG1_MCS0_32 :
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TX39_MEMCONFIG1_MCS1_32);
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tx_conf_write(tc, TX39_MEMCONFIG1_REG, reg);
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#endif /* TX392X */
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} else {
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/* CARD io/attr or mem */
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reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG);
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/* enable I/O access */
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reg |= (cs == TX39_CARD1) ?
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TX39_MEMCONFIG3_CARD1IOEN :
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TX39_MEMCONFIG3_CARD2IOEN;
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/* disable 8bit access */
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#ifdef TX392X
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reg &= ~((cs == TX39_CARD1) ?
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TX39_MEMCONFIG3_CARD1_8SEL :
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TX39_MEMCONFIG3_CARD2_8SEL);
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#endif /* TX392X */
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#ifdef TX391X
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reg &= ~TX39_MEMCONFIG3_PORT8SEL;
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#endif /* TX391X */
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tx_conf_write(tc, TX39_MEMCONFIG3_REG, reg);
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}
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break;
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case 8:
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if (TX39_ISCARD(cs)) {
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reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG);
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/* enable I/O access */
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reg |= (cs == TX39_CARD1) ?
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TX39_MEMCONFIG3_CARD1IOEN :
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TX39_MEMCONFIG3_CARD2IOEN;
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/* disable 8bit access */
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#ifdef TX392X
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reg |= (cs == TX39_CARD1) ?
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TX39_MEMCONFIG3_CARD1_8SEL :
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TX39_MEMCONFIG3_CARD2_8SEL;
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#endif /* TX392X */
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#ifdef TX391X
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reg |= TX39_MEMCONFIG3_PORT8SEL;
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#endif /* TX391X */
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tx_conf_write(tc, TX39_MEMCONFIG3_REG, reg);
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} else {
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panic("__txcsbus_alloc_cstag: CS%d 8bit mode is"
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"not allowed", cs);
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}
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}
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return (&iot->bst);
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}
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