d9c7f72cf3
This is for sure the most overkill hardware I've ever seen! For example, it needs the VAX page tables so that it can access all data structures and mbufs in virtual memory! It will be a real challenge to make this device work on mips and Alpha systems :-)
863 lines
21 KiB
C
863 lines
21 KiB
C
/* $NetBSD: if_ni.c,v 1.1 2000/04/09 16:49:57 ragge Exp $ */
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/*
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* Copyright (c) 2000 Ludd, University of Lule}, Sweden. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed at Ludd, University of
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* Lule}, Sweden and its contributors.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Driver for DEBNA/DEBNT/DEBNK ethernet cards.
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* Things that is still to do:
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* Collect statistics.
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*/
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#include "opt_inet.h"
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#include "bpfilter.h"
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#include <sys/param.h>
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#include <sys/mbuf.h>
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#include <sys/socket.h>
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#include <sys/device.h>
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#include <sys/systm.h>
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#include <sys/sockio.h>
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#include <net/if.h>
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#include <net/if_ether.h>
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#include <net/if_dl.h>
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#include <netinet/in.h>
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#include <netinet/if_inarp.h>
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#if NBPFILTER > 0
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#include <net/bpf.h>
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#include <net/bpfdesc.h>
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#endif
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#include <machine/bus.h>
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#ifdef __vax__
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#include <machine/mtpr.h>
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#include <machine/pte.h>
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#endif
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#include <dev/bi/bireg.h>
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#include <dev/bi/bivar.h>
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#include "ioconf.h"
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#include "locators.h"
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/*
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* Tunable buffer parameters. Good idea to have them as power of 8; then
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* they will fit into a logical VAX page.
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*/
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#define NMSGBUF 8 /* Message queue entries */
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#define NTXBUF 16 /* Transmit queue entries */
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#define NTXFRAGS 8 /* Number of transmit buffer fragments */
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#define NRXBUF 24 /* Receive queue entries */
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#define NBDESCS (NTXBUF * NTXFRAGS + NRXBUF)
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#define NQUEUES 3 /* RX + TX + MSG */
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#define PKTHDR 18 /* Length of (control) packet header */
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#define RXADD 18 /* Additional length of receive datagram */
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#define TXADD (10+NTXFRAGS*8) /* "" transmit "" */
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#define MSGADD 134 /* "" message "" */
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#include <dev/bi/if_nireg.h> /* XXX include earlier */
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/*
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* Macros for (most cases of) insqti/remqhi.
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* Retry NRETRIES times to do the operation, if it still fails assume
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* a lost lock and panic.
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*/
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#define NRETRIES 100
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#define INSQTI(e, h) ({ \
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int ret, i; \
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for (i = 0; i < NRETRIES; i++) { \
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if ((ret = insqti(e, h)) != ILCK_FAILED) \
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break; \
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} \
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if (i == NRETRIES) \
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panic("ni: insqti failed at %d", __LINE__); \
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ret; \
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})
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#define REMQHI(h) ({ \
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int i;void *ret; \
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for (i = 0; i < NRETRIES; i++) { \
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if ((ret = remqhi(h)) != (void *)ILCK_FAILED) \
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break; \
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} \
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if (i == NRETRIES) \
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panic("ni: remqhi failed at %d", __LINE__); \
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ret; \
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})
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#define nipqb (&sc->sc_gvppqb->nc_pqb)
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#define gvp sc->sc_gvppqb
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#define fqb sc->sc_fqb
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#define bbd sc->sc_bbd
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struct ni_softc {
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struct device sc_dev; /* Configuration common part */
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struct ethercom sc_ec; /* Ethernet common part */
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#define sc_if sc_ec.ec_if /* network-visible interface */
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bus_space_tag_t sc_iot;
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bus_addr_t sc_ioh;
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bus_dma_tag_t sc_dmat;
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struct ni_gvppqb *sc_gvppqb; /* Port queue block */
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struct ni_gvppqb *sc_pgvppqb; /* Phys address of PQB */
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struct ni_fqb *sc_fqb; /* Free Queue block */
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struct ni_bbd *sc_bbd; /* Buffer descriptors */
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u_int8_t sc_enaddr[ETHER_ADDR_LEN];
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};
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static int nimatch __P((struct device *, struct cfdata *, void *));
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static void niattach __P((struct device *, struct device *, void *));
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static void niinit __P((struct ni_softc *));
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static void nistart __P((struct ifnet *));
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static void niintr __P((void *));
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static int niioctl __P((struct ifnet *, u_long, caddr_t));
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static int ni_add_rxbuf(struct ni_softc *, struct ni_dg *, int);
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static void ni_setup __P((struct ni_softc *));
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static void nitimeout __P((struct ifnet *));
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static void ni_getpgs(struct ni_softc *sc, int size, caddr_t *v, paddr_t *p);
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volatile int endwait; /* Used during autoconfig */
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struct cfattach ni_ca = {
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sizeof(struct ni_softc), nimatch, niattach
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};
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#define NI_WREG(csr, val) \
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, csr, val)
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#define NI_RREG(csr) \
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bus_space_read_4(sc->sc_iot, sc->sc_ioh, csr)
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#define WAITREG(csr,val) while (NI_RREG(csr) & val);
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/*
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* Check for present device.
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*/
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int
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nimatch(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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struct bi_attach_args *ba = aux;
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u_short type;
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type = bus_space_read_2(ba->ba_iot, ba->ba_ioh, BIREG_DTYPE);
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if (type != BIDT_DEBNA && type != BIDT_DEBNT && type != BIDT_DEBNK)
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return 0;
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if (cf->cf_loc[BICF_NODE] != BICF_NODE_DEFAULT &&
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cf->cf_loc[BICF_NODE] != ba->ba_nodenr)
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return 0;
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return 1;
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}
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/*
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* Allocate a bunch of descriptor-safe memory.
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* We need to get the structures from the beginning of its own pages.
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*/
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static void
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ni_getpgs(struct ni_softc *sc, int size, caddr_t *v, paddr_t *p)
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{
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bus_dma_segment_t seg;
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int nsegs, error;
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if ((error = bus_dmamem_alloc(sc->sc_dmat, size, NBPG, 0, &seg, 1,
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&nsegs, BUS_DMA_NOWAIT)) != 0)
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panic(" unable to allocate memory: error %d", error);
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if ((error = bus_dmamem_map(sc->sc_dmat, &seg, nsegs, size, v,
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BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0)
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panic(" unable to map memory: error %d", error);
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if (p)
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*p = seg.ds_addr;
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}
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/*
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* Interface exists: make available by filling in network interface
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* record. System will initialize the interface when it is ready
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* to accept packets.
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*/
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void
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niattach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct bi_attach_args *ba = aux;
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struct ni_softc *sc = (struct ni_softc *)self;
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struct ifnet *ifp = (struct ifnet *)&sc->sc_if;
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struct ni_msg *msg;
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struct ni_ptdb *ptdb;
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caddr_t va;
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int i, j, res;
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u_short type;
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type = bus_space_read_2(ba->ba_iot, ba->ba_ioh, BIREG_DTYPE);
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printf(": DEBN%c\n", type == BIDT_DEBNA ? 'A' : type == BIDT_DEBNT ?
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'T' : 'K');
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sc->sc_iot = ba->ba_iot;
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sc->sc_ioh = ba->ba_ioh;
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sc->sc_dmat = ba->ba_dmat;
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bi_intr_establish(ba->ba_icookie, ba->ba_ivec, niintr, sc);
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ni_getpgs(sc, sizeof(struct ni_gvppqb), (caddr_t *)&sc->sc_gvppqb,
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(paddr_t *)&sc->sc_pgvppqb);
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ni_getpgs(sc, sizeof(struct ni_fqb), (caddr_t *)&sc->sc_fqb, 0);
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ni_getpgs(sc, NBDESCS * sizeof(struct ni_bbd),
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(caddr_t *)&sc->sc_bbd, 0);
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/*
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* Zero the newly allocated memory.
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*/
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bzero(sc->sc_gvppqb, sizeof(struct ni_gvppqb));
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nipqb->np_veclvl = (ba->ba_ivec << 2) + 2;
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nipqb->np_node = ba->ba_intcpu;
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nipqb->np_vpqb = (u_int32_t)gvp;
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#ifdef __vax__
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nipqb->np_spt = nipqb->np_gpt = mfpr(PR_SBR);
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nipqb->np_sptlen = nipqb->np_gptlen = mfpr(PR_SLR);
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#else
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#error Must fix support for non-vax.
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#endif
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nipqb->np_bvplvl = 1;
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nipqb->np_vfqb = (u_int32_t)fqb;
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nipqb->np_vbdt = (u_int32_t)bbd;
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nipqb->np_nbdr = NBDESCS;
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/* Free queue block */
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nipqb->np_freeq = NQUEUES;
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fqb->nf_mlen = PKTHDR+MSGADD;
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fqb->nf_dlen = PKTHDR+TXADD;
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fqb->nf_rlen = PKTHDR+RXADD;
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strcpy(ifp->if_xname, sc->sc_dev.dv_xname);
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ifp->if_softc = sc;
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ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
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ifp->if_start = nistart;
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ifp->if_ioctl = niioctl;
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ifp->if_watchdog = nitimeout;
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/*
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* Start init sequence.
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*/
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/* Check state */
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for (i = 0; i < 100; i++) {
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if ((NI_RREG(NI_PSR) & PSR_STATE) == PSR_UNDEF)
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break;
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DELAY(100000);
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}
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if (i == 100) {
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printf(": not undefined state\n");
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return;
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}
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/* Clear owner bits */
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NI_WREG(NI_PSR, NI_RREG(NI_PSR) & ~PSR_OWN);
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NI_WREG(NI_PCR, NI_RREG(NI_PCR) & ~PCR_OWN);
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/* kick off init */
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NI_WREG(NI_PCR, (u_int32_t)sc->sc_pgvppqb | PCR_INIT | PCR_OWN);
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while (NI_RREG(NI_PCR) & PCR_OWN)
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DELAY(100000);
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/* Check state */
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for (i = 0; i < 100; i++) {
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if ((NI_RREG(NI_PSR) & PSR_INITED))
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break;
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DELAY(100000);
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}
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if (i == 100) {
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printf(": failed initialize\n");
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return;
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}
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NI_WREG(NI_PSR, NI_RREG(NI_PSR) & ~PSR_OWN);
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WAITREG(NI_PCR, PCR_OWN);
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NI_WREG(NI_PCR, PCR_OWN|PCR_ENABLE);
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WAITREG(NI_PCR, PCR_OWN);
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WAITREG(NI_PSR, PSR_OWN);
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/* Check state */
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for (i = 0; i < 100; i++) {
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if ((NI_RREG(NI_PSR) & PSR_STATE) == PSR_ENABLED)
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break;
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DELAY(10000);
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}
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if (i == 100) {
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printf(": failed enable\n");
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return;
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}
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NI_WREG(NI_PSR, NI_RREG(NI_PSR) & ~PSR_OWN);
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/*
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* The message queue packets must be located on the beginning
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* of a page. A VAX page is 512 bytes, but it clusters 8 pages.
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* This knowledge is used here when allocating pages.
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* !!! How should this be done on MIPS and Alpha??? !!!
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*/
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#if NBPG < 4096
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#error pagesize too small
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#endif
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/* Set up message free queue */
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ni_getpgs(sc, NMSGBUF * 512, &va, 0);
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bzero(va, NMSGBUF * 512);
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for (i = 0; i < NMSGBUF; i++) {
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struct ni_msg *msg;
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msg = (void *)(va + i * 512);
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res = INSQTI(msg, &fqb->nf_mforw);
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}
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WAITREG(NI_PCR, PCR_OWN);
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NI_WREG(NI_PCR, PCR_FREEQNE|PCR_MFREEQ|PCR_OWN);
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WAITREG(NI_PCR, PCR_OWN);
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/* Set up xmit queue */
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ni_getpgs(sc, NTXBUF * 512, &va, 0);
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for (i = 0; i < NTXBUF; i++) {
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struct ni_dg *data;
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data = (void *)(va + i * 512);
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data->nd_status = 0;
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data->nd_len = TXADD;
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data->nd_ptdbidx = 1;
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data->nd_opcode = BVP_DGRAM;
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for (j = 0; j < NTXFRAGS; j++) {
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data->bufs[j]._offset = 0;
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data->bufs[j]._key = 1;
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bbd[i * NTXFRAGS + j].nb_key = 1;
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bbd[i * NTXFRAGS + j].nb_status = 0;
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data->bufs[j]._index = i * NTXFRAGS + j;
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}
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res = INSQTI(data, &fqb->nf_dforw);
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}
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WAITREG(NI_PCR, PCR_OWN);
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NI_WREG(NI_PCR, PCR_FREEQNE|PCR_DFREEQ|PCR_OWN);
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WAITREG(NI_PCR, PCR_OWN);
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/* recv buffers */
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ni_getpgs(sc, NRXBUF * 512, &va, 0);
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for (i = 0; i < NRXBUF; i++) {
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struct ni_dg *data;
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int idx;
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data = (void *)(va + i * 512);
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data->nd_len = RXADD;
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data->nd_opcode = BVP_DGRAMRX;
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data->nd_ptdbidx = 2;
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data->bufs[0]._key = 1;
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idx = NTXBUF * NTXFRAGS + i;
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if (ni_add_rxbuf(sc, data, idx))
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panic("niattach: ni_add_rxbuf: out of mbufs");
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res = INSQTI(data, &fqb->nf_rforw);
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}
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WAITREG(NI_PCR, PCR_OWN);
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NI_WREG(NI_PCR, PCR_FREEQNE|PCR_RFREEQ|PCR_OWN);
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WAITREG(NI_PCR, PCR_OWN);
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/* Set initial parameters */
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msg = REMQHI(&fqb->nf_mforw);
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msg->nm_opcode = BVP_MSG;
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msg->nm_status = 0;
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msg->nm_len = sizeof(struct ni_param) + 6;
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msg->nm_opcode2 = NI_WPARAM;
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((struct ni_param *)&msg->nm_text[0])->np_flags = NP_PAD;
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endwait = 0;
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res = INSQTI(msg, &gvp->nc_forw0);
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WAITREG(NI_PCR, PCR_OWN);
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NI_WREG(NI_PCR, PCR_CMDQNE|PCR_CMDQ0|PCR_OWN);
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WAITREG(NI_PCR, PCR_OWN);
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while (endwait == 0)
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;
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/* Clear counters */
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msg = REMQHI(&fqb->nf_mforw);
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msg->nm_opcode = BVP_MSG;
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msg->nm_status = 0;
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msg->nm_len = sizeof(struct ni_param) + 6;
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msg->nm_opcode2 = NI_RCCNTR;
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res = INSQTI(msg, &gvp->nc_forw0);
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WAITREG(NI_PCR, PCR_OWN);
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NI_WREG(NI_PCR, PCR_CMDQNE|PCR_CMDQ0|PCR_OWN);
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WAITREG(NI_PCR, PCR_OWN);
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/* Enable transmit logic */
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msg = REMQHI(&fqb->nf_mforw);
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msg->nm_opcode = BVP_MSG;
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msg->nm_status = 0;
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msg->nm_len = 18;
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msg->nm_opcode2 = NI_STPTDB;
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ptdb = (struct ni_ptdb *)&msg->nm_text[0];
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bzero(ptdb, sizeof(struct ni_ptdb));
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ptdb->np_index = 1;
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ptdb->np_fque = 1;
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res = INSQTI(msg, &gvp->nc_forw0);
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WAITREG(NI_PCR, PCR_OWN);
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NI_WREG(NI_PCR, PCR_CMDQNE|PCR_CMDQ0|PCR_OWN);
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WAITREG(NI_PCR, PCR_OWN);
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/* Wait for everything to finish */
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WAITREG(NI_PSR, PSR_OWN);
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printf("%s: hardware address %s\n", sc->sc_dev.dv_xname,
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ether_sprintf(sc->sc_enaddr));
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/*
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* Attach the interface.
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*/
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if_attach(ifp);
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ether_ifattach(ifp, sc->sc_enaddr);
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#if NBPFILTER > 0
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bpfattach(&ifp->if_bpf, ifp, DLT_EN10MB, sizeof(struct ether_header));
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#endif
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}
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/*
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* Initialization of interface.
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*/
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void
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niinit(sc)
|
|
struct ni_softc *sc;
|
|
{
|
|
struct ifnet *ifp = (struct ifnet *)&sc->sc_if;
|
|
|
|
/*
|
|
* Set flags (so ni_setup() do the right thing).
|
|
*/
|
|
ifp->if_flags |= IFF_RUNNING;
|
|
ifp->if_flags &= ~IFF_OACTIVE;
|
|
|
|
/*
|
|
* Send setup messages so that the rx/tx locic starts.
|
|
*/
|
|
ni_setup(sc);
|
|
|
|
}
|
|
|
|
/*
|
|
* Start output on interface.
|
|
*/
|
|
void
|
|
nistart(ifp)
|
|
struct ifnet *ifp;
|
|
{
|
|
struct ni_softc *sc = ifp->if_softc;
|
|
struct ni_dg *data;
|
|
struct ni_bbd *bdp;
|
|
struct mbuf *m, *m0;
|
|
int i, cnt, res, mlen;
|
|
|
|
if (ifp->if_flags & IFF_OACTIVE)
|
|
return;
|
|
#ifdef DEBUG
|
|
if (ifp->if_flags & IFF_DEBUG)
|
|
printf("%s: nistart\n", sc->sc_dev.dv_xname);
|
|
#endif
|
|
|
|
while (fqb->nf_dforw) {
|
|
IF_DEQUEUE(&sc->sc_if.if_snd, m);
|
|
if (m == 0)
|
|
break;
|
|
|
|
data = REMQHI(&fqb->nf_dforw);
|
|
if ((int)data == Q_EMPTY) {
|
|
IF_PREPEND(&sc->sc_if.if_snd, m);
|
|
ifp->if_flags |= IFF_OACTIVE;
|
|
break;
|
|
}
|
|
|
|
/*
|
|
* Count number of mbufs in chain.
|
|
* Always do DMA directly from mbufs, therefore the transmit
|
|
* ring is really big.
|
|
*/
|
|
for (m0 = m, cnt = 0; m0; m0 = m0->m_next)
|
|
if (m0->m_len)
|
|
cnt++;
|
|
if (cnt > NTXFRAGS)
|
|
panic("nistart"); /* XXX */
|
|
|
|
#if NBPFILTER > 0
|
|
if (ifp->if_bpf)
|
|
bpf_mtap(ifp->if_bpf, m);
|
|
#endif
|
|
bdp = &bbd[(data->bufs[0]._index & 0x7fff)];
|
|
for (m0 = m, i = 0, mlen = 0; m0; m0 = m0->m_next) {
|
|
if (m0->m_len == 0)
|
|
continue;
|
|
bdp->nb_status = (mtod(m0, u_int32_t) & NIBD_OFFSET) |
|
|
NIBD_VALID;
|
|
bdp->nb_pte = (u_int32_t)kvtopte(mtod(m0, void *));
|
|
bdp->nb_len = m0->m_len;
|
|
data->bufs[i]._offset = 0;
|
|
data->bufs[i]._len = bdp->nb_len;
|
|
data->bufs[i]._index |= NIDG_CHAIN;
|
|
mlen += bdp->nb_len;
|
|
bdp++;
|
|
i++;
|
|
}
|
|
data->nd_opcode = BVP_DGRAM;
|
|
data->nd_pad3 = 1;
|
|
data->nd_ptdbidx = 1;
|
|
data->nd_len = 10 + i * 8;
|
|
data->bufs[i - 1]._index &= ~NIDG_CHAIN;
|
|
if (mlen < 64)
|
|
data->bufs[i - 1]._len = bdp[-1].nb_len += (64 - mlen);
|
|
data->nd_cmdref = (u_int32_t)m;
|
|
#ifdef DEBUG
|
|
if (ifp->if_flags & IFF_DEBUG)
|
|
printf("%s: sending %d bytes (%d segments)\n",
|
|
sc->sc_dev.dv_xname, mlen, i);
|
|
#endif
|
|
|
|
res = INSQTI(data, &gvp->nc_forw0);
|
|
if (res == Q_EMPTY) {
|
|
WAITREG(NI_PCR, PCR_OWN);
|
|
NI_WREG(NI_PCR, PCR_CMDQNE|PCR_CMDQ0|PCR_OWN);
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
niintr(void *arg)
|
|
{
|
|
struct ether_header *eh;
|
|
struct ni_softc *sc = arg;
|
|
struct ni_dg *data;
|
|
struct ni_msg *msg;
|
|
struct ifnet *ifp = &sc->sc_if;
|
|
struct ni_bbd *bd;
|
|
struct mbuf *m;
|
|
int idx, res;
|
|
|
|
/* Got any response packets? */
|
|
while ((NI_RREG(NI_PSR) & PSR_RSQ) && (data = REMQHI(&gvp->nc_forwr))) {
|
|
|
|
switch (data->nd_opcode) {
|
|
case BVP_DGRAMRX: /* Receive datagram */
|
|
idx = data->bufs[0]._index;
|
|
bd = &bbd[idx];
|
|
m = (void *)data->nd_cmdref;
|
|
m->m_pkthdr.len = m->m_len = data->bufs[0]._len;
|
|
m->m_pkthdr.rcvif = ifp;
|
|
if (ni_add_rxbuf(sc, data, idx)) {
|
|
bd->nb_len = (m->m_ext.ext_size - 2);
|
|
bd->nb_pte =
|
|
(long)kvtopte(m->m_ext.ext_buf);
|
|
bd->nb_status = 2 | NIBD_VALID;
|
|
bd->nb_key = 1;
|
|
}
|
|
data->nd_len = RXADD;
|
|
data->nd_status = 0;
|
|
res = INSQTI(data, &fqb->nf_rforw);
|
|
if (res == Q_EMPTY) {
|
|
WAITREG(NI_PCR, PCR_OWN);
|
|
NI_WREG(NI_PCR, PCR_FREEQNE|PCR_RFREEQ|PCR_OWN);
|
|
}
|
|
if (m == (void *)data->nd_cmdref)
|
|
break; /* Out of mbufs */
|
|
|
|
#if NBPFILTER > 0
|
|
eh = mtod(m, struct ether_header *);
|
|
if (ifp->if_bpf) {
|
|
bpf_mtap(ifp->if_bpf, m);
|
|
if ((ifp->if_flags & IFF_PROMISC) != 0
|
|
&& bcmp(LLADDR(ifp->if_sadl),
|
|
eh->ether_dhost,
|
|
ETHER_ADDR_LEN) != 0 &&
|
|
((eh->ether_dhost[0] & 1) == 0)) {
|
|
m_freem(m);
|
|
continue;
|
|
}
|
|
}
|
|
#endif
|
|
(*ifp->if_input)(ifp, m);
|
|
break;
|
|
|
|
case BVP_DGRAM:
|
|
m = (struct mbuf *)data->nd_cmdref;
|
|
ifp->if_flags &= ~IFF_OACTIVE;
|
|
m_freem(m);
|
|
res = INSQTI(data, &fqb->nf_dforw);
|
|
if (res == Q_EMPTY) {
|
|
WAITREG(NI_PCR, PCR_OWN);
|
|
NI_WREG(NI_PCR, PCR_FREEQNE|PCR_DFREEQ|PCR_OWN);
|
|
}
|
|
break;
|
|
|
|
case BVP_MSGRX:
|
|
msg = (struct ni_msg *)data;
|
|
switch (msg->nm_opcode2) {
|
|
case NI_WPARAM:
|
|
bcopy(((struct ni_param *)&msg->nm_text[0])->np_dpa, sc->sc_enaddr, ETHER_ADDR_LEN);
|
|
endwait = 1;
|
|
break;
|
|
|
|
case NI_RCCNTR:
|
|
case NI_CLPTDB:
|
|
case NI_STPTDB:
|
|
break;
|
|
|
|
default:
|
|
printf("Unkn resp %d\n",
|
|
msg->nm_opcode2);
|
|
break;
|
|
}
|
|
res = INSQTI(data, &fqb->nf_mforw);
|
|
if (res == Q_EMPTY) {
|
|
WAITREG(NI_PCR, PCR_OWN);
|
|
NI_WREG(NI_PCR, PCR_FREEQNE|PCR_MFREEQ|PCR_OWN);
|
|
}
|
|
break;
|
|
|
|
default:
|
|
printf("Unknown opcode %d\n", data->nd_opcode);
|
|
res = INSQTI(data, &fqb->nf_mforw);
|
|
if (res == Q_EMPTY) {
|
|
WAITREG(NI_PCR, PCR_OWN);
|
|
NI_WREG(NI_PCR, PCR_FREEQNE|PCR_MFREEQ|PCR_OWN);
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Try to kick on the start routine again */
|
|
nistart(ifp);
|
|
|
|
NI_WREG(NI_PSR, NI_RREG(NI_PSR) & ~(PSR_OWN|PSR_RSQ));
|
|
}
|
|
|
|
/*
|
|
* Process an ioctl request.
|
|
*/
|
|
int
|
|
niioctl(ifp, cmd, data)
|
|
register struct ifnet *ifp;
|
|
u_long cmd;
|
|
caddr_t data;
|
|
{
|
|
struct ni_softc *sc = ifp->if_softc;
|
|
struct ifreq *ifr = (struct ifreq *)data;
|
|
struct ifaddr *ifa = (struct ifaddr *)data;
|
|
int s = splnet(), error = 0;
|
|
|
|
switch (cmd) {
|
|
|
|
case SIOCSIFADDR:
|
|
ifp->if_flags |= IFF_UP;
|
|
switch(ifa->ifa_addr->sa_family) {
|
|
#ifdef INET
|
|
case AF_INET:
|
|
niinit(sc);
|
|
arp_ifinit(ifp, ifa);
|
|
break;
|
|
#endif
|
|
}
|
|
break;
|
|
|
|
case SIOCSIFFLAGS:
|
|
if ((ifp->if_flags & IFF_UP) == 0 &&
|
|
(ifp->if_flags & IFF_RUNNING) != 0) {
|
|
/*
|
|
* If interface is marked down and it is running,
|
|
* stop it.
|
|
*/
|
|
ifp->if_flags &= ~IFF_RUNNING;
|
|
ni_setup(sc);
|
|
} else if ((ifp->if_flags & IFF_UP) != 0 &&
|
|
(ifp->if_flags & IFF_RUNNING) == 0) {
|
|
/*
|
|
* If interface it marked up and it is stopped, then
|
|
* start it.
|
|
*/
|
|
niinit(sc);
|
|
} else if ((ifp->if_flags & IFF_UP) != 0) {
|
|
/*
|
|
* Send a new setup packet to match any new changes.
|
|
* (Like IFF_PROMISC etc)
|
|
*/
|
|
ni_setup(sc);
|
|
}
|
|
break;
|
|
|
|
case SIOCADDMULTI:
|
|
case SIOCDELMULTI:
|
|
/*
|
|
* Update our multicast list.
|
|
*/
|
|
error = (cmd == SIOCADDMULTI) ?
|
|
ether_addmulti(ifr, &sc->sc_ec):
|
|
ether_delmulti(ifr, &sc->sc_ec);
|
|
|
|
if (error == ENETRESET) {
|
|
/*
|
|
* Multicast list has changed; set the hardware filter
|
|
* accordingly.
|
|
*/
|
|
ni_setup(sc);
|
|
error = 0;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
error = EINVAL;
|
|
|
|
}
|
|
splx(s);
|
|
return (error);
|
|
}
|
|
|
|
/*
|
|
* Add a receive buffer to the indicated descriptor.
|
|
*/
|
|
int
|
|
ni_add_rxbuf(struct ni_softc *sc, struct ni_dg *data, int idx)
|
|
{
|
|
struct ni_bbd *bd = &bbd[idx];
|
|
struct mbuf *m;
|
|
|
|
MGETHDR(m, M_DONTWAIT, MT_DATA);
|
|
if (m == NULL)
|
|
return (ENOBUFS);
|
|
|
|
MCLGET(m, M_DONTWAIT);
|
|
if ((m->m_flags & M_EXT) == 0) {
|
|
m_freem(m);
|
|
return (ENOBUFS);
|
|
}
|
|
|
|
m->m_data += 2;
|
|
bd->nb_len = (m->m_ext.ext_size - 2);
|
|
bd->nb_pte = (long)kvtopte(m->m_ext.ext_buf);
|
|
bd->nb_status = 2 | NIBD_VALID;
|
|
bd->nb_key = 1;
|
|
|
|
data->bufs[0]._offset = 0;
|
|
data->bufs[0]._len = bd->nb_len;
|
|
data->bufs[0]._index = idx;
|
|
data->nd_cmdref = (long)m;
|
|
|
|
return (0);
|
|
}
|
|
|
|
/*
|
|
* Create setup packet and put in queue for sending.
|
|
*/
|
|
void
|
|
ni_setup(struct ni_softc *sc)
|
|
{
|
|
struct ifnet *ifp = &sc->sc_if;
|
|
struct ni_msg *msg;
|
|
struct ni_ptdb *ptdb;
|
|
struct ether_multi *enm;
|
|
struct ether_multistep step;
|
|
int i, res;
|
|
|
|
msg = REMQHI(&fqb->nf_mforw);
|
|
if ((int)msg == Q_EMPTY)
|
|
return; /* What to do? */
|
|
|
|
ptdb = (struct ni_ptdb *)&msg->nm_text[0];
|
|
bzero(ptdb, sizeof(struct ni_ptdb));
|
|
|
|
msg->nm_opcode = BVP_MSG;
|
|
msg->nm_len = 18;
|
|
ptdb->np_index = 2; /* definition type index */
|
|
ptdb->np_fque = 2; /* Free queue */
|
|
if (ifp->if_flags & IFF_RUNNING) {
|
|
msg->nm_opcode2 = NI_STPTDB;
|
|
ptdb->np_type = ETHERTYPE_IP;
|
|
ptdb->np_flags = PTDB_UNKN|PTDB_BDC;
|
|
if (ifp->if_flags & IFF_PROMISC)
|
|
ptdb->np_flags |= PTDB_PROMISC;
|
|
memset(ptdb->np_mcast[0], 0xff, ETHER_ADDR_LEN); /* Broadcast */
|
|
ptdb->np_adrlen = 1;
|
|
msg->nm_len += 8;
|
|
ifp->if_flags &= ~IFF_ALLMULTI;
|
|
if ((ifp->if_flags & IFF_PROMISC) == 0) {
|
|
ETHER_FIRST_MULTI(step, &sc->sc_ec, enm);
|
|
i = 1;
|
|
while (enm != NULL) {
|
|
if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 6)) {
|
|
ifp->if_flags |= IFF_ALLMULTI;
|
|
ptdb->np_flags |= PTDB_AMC;
|
|
break;
|
|
}
|
|
msg->nm_len += 8;
|
|
ptdb->np_adrlen++;
|
|
bcopy(enm->enm_addrlo, ptdb->np_mcast[i++],
|
|
ETHER_ADDR_LEN);
|
|
ETHER_NEXT_MULTI(step, enm);
|
|
}
|
|
}
|
|
} else
|
|
msg->nm_opcode2 = NI_CLPTDB;
|
|
|
|
res = INSQTI(msg, &gvp->nc_forw0);
|
|
if (res == Q_EMPTY) {
|
|
WAITREG(NI_PCR, PCR_OWN);
|
|
NI_WREG(NI_PCR, PCR_CMDQNE|PCR_CMDQ0|PCR_OWN);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Check for dead transmit logic. Not uncommon.
|
|
*/
|
|
void
|
|
nitimeout(ifp)
|
|
struct ifnet *ifp;
|
|
{
|
|
#if 0
|
|
struct ni_softc *sc = ifp->if_softc;
|
|
|
|
if (sc->sc_inq == 0)
|
|
return;
|
|
|
|
printf("%s: xmit logic died, resetting...\n", sc->sc_dev.dv_xname);
|
|
/*
|
|
* Do a reset of interface, to get it going again.
|
|
* Will it work by just restart the transmit logic?
|
|
*/
|
|
niinit(sc);
|
|
#endif
|
|
}
|