d974db0ada
This branch was a major cleanup and rototill of many of the various OEA cpu based PPC ports that focused on sharing as much code as possible between the various ports to eliminate near-identical copies of files in every tree. Additionally there is a new PIC system that unifies the interface to interrupt code for all different OEA ppc arches. The work for this branch was done by a variety of people, too long to list here. TODO: bebox still needs work to complete the transition to -renovation. ofppc still needs a bunch of work, which I will be looking at. ev64260 still needs to be renovated amigappc was not attempted. NOTES: pmppc was removed as an arch, and moved to a evbppc target.
289 lines
7.8 KiB
C
289 lines
7.8 KiB
C
/* $NetBSD: pchb.c,v 1.2 2007/10/17 19:56:44 garbled Exp $ */
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/*-
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* Copyright (c) 2007 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Tim Rightnour
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pchb.c,v 1.2 2007/10/17 19:56:44 garbled Exp $");
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <machine/bus.h>
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#include <machine/pio.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/agpreg.h>
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#include <dev/pci/agpvar.h>
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#include <dev/ic/mpc105reg.h>
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#include <dev/ic/mpc106reg.h>
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#include <dev/ic/ibm82660reg.h>
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#include "agp.h"
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int pchbmatch(struct device *, struct cfdata *, void *);
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void pchbattach(struct device *, struct device *, void *);
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CFATTACH_DECL(pchb, sizeof(struct device),
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pchbmatch, pchbattach, NULL, NULL);
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int
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pchbmatch(struct device *parent, struct cfdata *cf, void *aux)
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{
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struct pci_attach_args *pa = aux;
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/*
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* Match all known PCI host chipsets.
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*/
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if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
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PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_HOST) {
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return (1);
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}
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return (0);
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}
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static void
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mpc105_print(struct pci_attach_args *pa, struct device *self)
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{
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pcireg_t reg1, reg2;
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const char *s1;
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reg1 = pci_conf_read(pa->pa_pc, pa->pa_tag, MPC105_PICR1);
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reg2 = pci_conf_read(pa->pa_pc, pa->pa_tag, MPC105_PICR2);
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aprint_normal("%s: L2 cache: ", self->dv_xname);
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switch (reg2 & MPC105_PICR2_L2_SIZE) {
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case MPC105_PICR2_L2_SIZE_256K:
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s1 = "256K";
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break;
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case MPC105_PICR2_L2_SIZE_512K:
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s1 = "512K";
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break;
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case MPC105_PICR2_L2_SIZE_1M:
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s1 = "1M";
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break;
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default:
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s1 = "reserved size";
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break;
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}
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aprint_normal("%s, ", s1);
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switch (reg1 & MPC105_PICR1_L2_MP) {
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case MPC105_PICR1_L2_MP_NONE:
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s1 = "uniprocessor/none";
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break;
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case MPC105_PICR1_L2_MP_WT:
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s1 = "write-through";
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break;
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case MPC105_PICR1_L2_MP_WB:
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s1 = "write-back";
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break;
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case MPC105_PICR1_L2_MP_MP:
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s1 = "multiprocessor";
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break;
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}
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aprint_normal("%s mode\n", s1);
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}
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static void
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mpc106_print(struct pci_attach_args *pa, struct device *self)
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{
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pcireg_t reg1, reg2;
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const char *s1;
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reg1 = pci_conf_read(pa->pa_pc, pa->pa_tag, MPC106_PICR1);
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reg2 = pci_conf_read(pa->pa_pc, pa->pa_tag, MPC106_PICR2);
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aprint_normal("%s: L2 cache: ", self->dv_xname);
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switch (reg2 & MPC106_PICR2_L2_SIZE) {
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case MPC106_PICR2_L2_SIZE_256K:
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s1 = "256K";
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break;
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case MPC106_PICR2_L2_SIZE_512K:
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s1 = "512K";
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break;
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case MPC106_PICR2_L2_SIZE_1M:
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s1 = "1M";
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break;
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default:
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s1 = "reserved size";
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break;
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}
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aprint_normal("%s, ", s1);
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switch (reg1 & MPC106_PICR1_EXT_L2_EN) {
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case 0:
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switch (reg1 & MPC106_PICR1_L2_MP) {
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case MPC106_PICR1_L2_MP_NONE:
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s1 = "uniprocessor/none";
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break;
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case MPC106_PICR1_L2_MP_WT:
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s1 = "internally controlled write-through";
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break;
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case MPC106_PICR1_L2_MP_WB:
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s1 = "internally controlled write-back";
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break;
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case MPC106_PICR1_L2_MP_MP:
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s1 = "multiprocessor/none";
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break;
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}
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break;
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case 1:
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switch (reg1 & MPC106_PICR1_L2_MP) {
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case MPC106_PICR1_L2_MP_NONE:
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s1 = "uniprocessor/external";
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break;
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case MPC106_PICR1_L2_MP_MP:
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s1 = "multiprocessors/external";
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break;
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default:
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s1 = "reserved";
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break;
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}
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}
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aprint_normal("%s mode\n", s1);
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}
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static void
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ibm82660_print(struct pci_attach_args *pa, struct device *self)
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{
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pcireg_t reg1;
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#ifdef PREP_BUS_SPACE_IO
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pcireg_t reg2;
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#endif
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const char *s1, *s2;
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reg1 = pci_conf_read(pa->pa_pc, pa->pa_tag,
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IBM_82660_CACHE_STATUS);
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#ifdef PREP_BUS_SPACE_IO
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reg2 = in32rb(PREP_BUS_SPACE_IO+IBM_82660_SYSTEM_CTRL);
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if (reg2 & IBM_82660_SYSTEM_CTRL_L2_EN) {
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if (reg1 & IBM_82660_CACHE_STATUS_L2_EN)
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s1 = "internal enabled";
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else
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s1 = "enabled";
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if (reg2 & IBM_82660_SYSTEM_CTRL_L2_MI)
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s2 = "(normal operation)";
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else
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s2 = "(miss updates inhibited)";
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} else {
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s1 = "disabled";
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s2 = "";
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}
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#else
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if (reg1 & IBM_82660_CACHE_STATUS_L2_EN)
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s1 = "enabled";
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else
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s1 = "disabled";
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s2 = "";
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#endif
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aprint_normal("%s: L1: %s L2: %s %s\n", self->dv_xname,
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(reg1 & IBM_82660_CACHE_STATUS_L1_EN) ? "enabled" : "disabled",
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s1, s2);
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reg1 = pci_conf_read(pa->pa_pc, pa->pa_tag, IBM_82660_OPTIONS_1);
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aprint_verbose("%s: MCP# assertion %s "
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"TEA# assertion %s\n", self->dv_xname,
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(reg1 & IBM_82660_OPTIONS_1_MCP) ? "enabled" : "disabled",
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(reg1 & IBM_82660_OPTIONS_1_TEA) ? "enabled" : "disabled");
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aprint_verbose("%s: PCI/ISA I/O mapping %s\n", self->dv_xname,
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(reg1 & IBM_82660_OPTIONS_1_ISA) ? "contiguous" : "non-contiguous");
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reg1 = pci_conf_read(pa->pa_pc, pa->pa_tag, IBM_82660_OPTIONS_3);
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aprint_normal("%s: DRAM %s (%s) SRAM %s\n", self->dv_xname,
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(reg1 & IBM_82660_OPTIONS_3_DRAM) ? "EDO" : "standard",
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(reg1 & IBM_82660_OPTIONS_3_ECC) ? "ECC" : "parity",
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(reg1 & IBM_82660_OPTIONS_3_SRAM) ? "sync" : "async");
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aprint_verbose("%s: Snoop mode %s\n", self->dv_xname,
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(reg1 & IBM_82660_OPTIONS_3_SNOOP) ? "603" : "601/604");
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}
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void
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pchbattach(struct device *parent, struct device *self, void *aux)
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{
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struct pci_attach_args *pa = aux;
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char devinfo[256];
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#if NAGP > 0
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struct agpbus_attach_args apa;
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#endif
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printf("\n");
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/*
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* All we do is print out a description. Eventually, we
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* might want to add code that does something that's
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* possibly chipset-specific.
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*/
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pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo));
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printf("%s: %s (rev. 0x%02x)\n", self->dv_xname, devinfo,
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PCI_REVISION(pa->pa_class));
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switch (PCI_VENDOR(pa->pa_id)) {
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case PCI_VENDOR_IBM:
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switch (PCI_PRODUCT(pa->pa_id)) {
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case PCI_PRODUCT_IBM_82660:
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ibm82660_print(pa, self);
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break;
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}
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break;
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case PCI_VENDOR_MOT:
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switch (PCI_PRODUCT(pa->pa_id)) {
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case PCI_PRODUCT_MOT_MPC105:
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mpc105_print(pa, self);
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break;
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case PCI_PRODUCT_MOT_MPC106:
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mpc106_print(pa, self);
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break;
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}
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break;
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}
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#if NAGP > 0
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if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP,
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NULL, NULL) != 0) {
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apa.apa_pci_args = *pa;
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config_found_ia(self, "agpbus", &apa, agpbusprint);
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}
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#endif /* NAGP */
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}
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