578 lines
23 KiB
C
578 lines
23 KiB
C
/* $NetBSD: ctlreg.h,v 1.4 1998/11/13 03:47:15 eeh Exp $ */
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/*
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* Copyright (c) 1996
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* The President and Fellows of Harvard College. All rights reserved.
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Harvard University.
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)ctlreg.h 8.1 (Berkeley) 6/11/93
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*/
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/*
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* Sun4u support by Eduardo Horvath
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* Changes Copyright (c) 1996 Eduardo Horvath
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* All rights reserved.
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*/
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/*
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* Sun 4u control registers. (includes address space definitions
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* and some registers in control space).
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*/
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/*
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* The Alternate address spaces.
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*
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* 0x00-0x7f are privileged
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* 0x80-0xff can be used by users
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*/
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#define ASI_LITTLE 0x08 /* This bit should make an ASI little endian */
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#define ASI_NUCLEUS 0x04 /* [4u] kernel address space */
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#define ASI_NUCLEUS_LITTLE 0x0c /* [4u] kernel address space, little endian */
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#define ASI_AS_IF_USER_PRIMARY 0x10 /* [4u] primary user address space */
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#define ASI_AS_IF_USER_SECONDARY 0x11 /* [4u] secondary user address space */
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#define ASI_PHYS_CACHED 0x14 /* [4u] MMU bypass to main memory */
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#define ASI_PHYS_NON_CACHED 0x15 /* [4u] MMU bypass to I/O location */
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#define ASI_AS_IF_USER_PRIMARY_LITTLE 0x18 /* [4u] primary user address space, little endian */
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#define ASI_AS_IF_USER_SECONDARY_LITTIE 0x19 /* [4u] secondary user address space, little endian */
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#define ASI_PHYS_CACHED_LITTLE 0x1c /* [4u] MMU bypass to main memory, little endian */
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#define ASI_PHYS_NON_CACHED_LITTLE 0x1d /* [4u] MMU bypass to I/O location, little endian */
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#define ASI_NUCLEUS_QUAD_LDD 0x24 /* [4u] use w/LDDA to load 128-bit item */
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#define ASI_NUCLEUS_QUAD_LDD_LITTLE 0x2c /* [4u] use w/LDDA to load 128-bit item, little endian */
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#define ASI_FLUSH_D_PAGE_PRIMARY 0x38 /* [4u] flush D-cache page using primary context */
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#define ASI_FLUSH_D_PAGE_SECONDARY 0x39 /* [4u] flush D-cache page using secondary context */
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#define ASI_FLUSH_D_CTX_PRIMARY 0x3a /* [4u] flush D-cache context using primary context */
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#define ASI_FLUSH_D_CTX_SECONDARY 0x3b /* [4u] flush D-cache context using secondary context */
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#define ASI_DCACHE_DATA 0x46 /* [4u] diagnostic access to D-cache data RAM */
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#define ASI_DCACHE_TAG 0x47 /* [4u] diagnostic access to D-cache tag RAM */
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#define ASI_INTR_DISPATCH_STATUS 0x48 /* [4u] interrupt dispatch status register */
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#define ASI_INTR_RECEIVE 0x49 /* [4u] interrupt receive status register */
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#define ASI_MID_REG 0x4a /* [4u] hardware config and MID */
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#define ASI_ERROR_EN_REG 0x4b /* [4u] asynchronous error enables */
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#define ASI_AFSR 0x4c /* [4u] asynchronous fault status register */
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#define ASI_AFAR 0x4d /* [4u] asynchronous fault address register */
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#define ASI_ICACHE_DATA 0x66 /* [4u] diagnostic access to D-cache data RAM */
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#define ASI_ICACHE_TAG 0x67 /* [4u] diagnostic access to D-cache tag RAM */
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#define ASI_FLUSH_I_PAGE_PRIMARY 0x68 /* [4u] flush D-cache page using primary context */
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#define ASI_FLUSH_I_PAGE_SECONDARY 0x69 /* [4u] flush D-cache page using secondary context */
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#define ASI_FLUSH_I_CTX_PRIMARY 0x6a /* [4u] flush D-cache context using primary context */
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#define ASI_FLUSH_I_CTX_SECONDARY 0x6b /* [4u] flush D-cache context using secondary context */
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#define ASI_BLOCK_AS_IF_USER_PRIMARY 0x70 /* [4u] primary user address space, block loads/stores */
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#define ASI_BLOCK_AS_IF_USER_SECONDARY 0x71 /* [4u] secondary user address space, block loads/stores */
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#define ASI_ECACHE_DIAG 0x76 /* [4u] diag access to E-cache tag and data */
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#define ASI_DATAPATH_ERR_REG_WRITE 0x77 /* [4u] ASI is reused */
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#define ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 0x78 /* [4u] primary user address space, block loads/stores */
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#define ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 0x79 /* [4u] secondary user address space, block loads/stores */
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#define ASI_INTERRUPT_RECEIVE_DATA 0x7f /* [4u] interrupt receive data registers {0,1,2} */
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#define ASI_DATAPATH_ERR_REG_READ 0x7f /* [4u] read access to datapath error registers (ASI reused) */
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#define ASI_PRIMARY 0x80 /* [4u] primary address space */
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#define ASI_SECONDARY 0x81 /* [4u] secondary address space */
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#define ASI_PRIMARY_NO_FAULT 0x82 /* [4u] primary address space, no fault */
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#define ASI_SECONDARY_NO_FAULT 0x83 /* [4u] secondary address space, no fault */
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#define ASI_PRIMARY_LITTLE 0x88 /* [4u] primary address space, little endian */
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#define ASI_SECONDARY_LITTLE 0x89 /* [4u] secondary address space, little endian */
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#define ASI_PRIMARY_NO_FAULT_LITTLE 0x8a /* [4u] primary address space, no fault, little endian */
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#define ASI_SECONDARY_NO_FAULT_LITTLE 0x8b /* [4u] secondary address space, no fault, little endian */
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#define ASI_PST8_PRIMARY 0xc0 /* [VIS] Eight 8-bit partial store, primary */
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#define ASI_PST8_SECONDARY 0xc1 /* [VIS] Eight 8-bit partial store, secondary */
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#define ASI_PST16_PRIMARY 0xc2 /* [VIS] Four 16-bit partial store, primary */
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#define ASI_PST16_SECONDARY 0xc3 /* [VIS] Fout 16-bit partial store, secondary */
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#define ASI_PST32_PRIMARY 0xc4 /* [VIS] Two 32-bit partial store, primary */
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#define ASI_PST32_SECONDARY 0xc5 /* [VIS] Two 32-bit partial store, secondary */
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#define ASI_PST8_PRIMARY_LITTLE 0xc8 /* [VIS] Eight 8-bit partial store, primary, little endian */
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#define ASI_PST8_SECONDARY_LITTLE 0xc9 /* [VIS] Eight 8-bit partial store, secondary, little endian */
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#define ASI_PST16_PRIMARY_LITTLE 0xca /* [VIS] Four 16-bit partial store, primary, little endian */
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#define ASI_PST16_SECONDARY_LITTLE 0xcb /* [VIS] Fout 16-bit partial store, secondary, little endian */
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#define ASI_PST32_PRIMARY_LITTLE 0xcc /* [VIS] Two 32-bit partial store, primary, little endian */
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#define ASI_PST32_SECONDARY_LITTLE 0xcd /* [VIS] Two 32-bit partial store, secondary, little endian */
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#define ASI_FL8_PRIMARY 0xd0 /* [VIS] One 8-bit load/store floating, primary */
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#define ASI_FL8_SECONDARY 0xd1 /* [VIS] One 8-bit load/store floating, secondary */
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#define ASI_FL16_PRIMARY 0xd2 /* [VIS] One 16-bit load/store floating, primary */
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#define ASI_FL16_SECONDARY 0xd3 /* [VIS] One 16-bit load/store floating, secondary */
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#define ASI_FL8_PRIMARY_LITTLE 0xd8 /* [VIS] One 8-bit load/store floating, primary, little endian */
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#define ASI_FL8_SECONDARY_LITTLE 0xd9 /* [VIS] One 8-bit load/store floating, secondary, little endian */
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#define ASI_FL16_PRIMARY_LITTLE 0xda /* [VIS] One 16-bit load/store floating, primary, little endian */
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#define ASI_FL16_SECONDARY_LITTLE 0xdb /* [VIS] One 16-bit load/store floating, secondary, little endian */
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#define ASI_BLOCK_COMMIT_PRIMARY 0xe0 /* [4u] block store with commit, primary */
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#define ASI_BLOCK_COMMIT_SECONDARY 0xe1 /* [4u] block store with commit, secondary */
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#define ASI_BLOCK_PRIMARY 0xf0 /* [4u] block load/store, primary */
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#define ASI_BLOCK_SECONDARY 0xf1 /* [4u] block load/store, secondary */
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#define ASI_BLOCK_PRIMARY_LITTLE 0xf8 /* [4u] block load/store, primary, little endian */
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#define ASI_BLOCK_SECONDARY_LITTLE 0xf9 /* [4u] block load/store, secondary, little endian */
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/*
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* These are the shorter names used by Solaris
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*/
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#define ASI_N ASI_NUCLEUS
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#define ASI_NL ASI_NUCLEUS_LITTLE
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#define ASI_AIUP ASI_AS_IF_USER_PRIMARY
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#define ASI_AIUS ASI_AS_IF_USER_SECONDARY
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#define ASI_AIUPL ASI_AS_IF_USER_PRIMARY_LITTLE
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#define ASI_AIUSL ASI_AS_IF_USER_SECONDARY_LITTLE
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#define ASI_P ASI_PRIMARY
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#define ASI_S ASI_SECONDARY
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#define ASI_PNF ASI_PRIMARY_NO_FAULT
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#define ASI_SNF ASI_SECONDARY_NO_FAULT
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#define ASI_PL ASI_PRIMARY_LITTLE
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#define ASI_SL ASI_SECONDARY_LITTLE
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#define ASI_PNFL ASI_PRIMARY_NO_FAULT_LITTLE
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#define ASI_SNFL ASI_SECONDARY_NO_FAULT_LITTLE
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#define ASI_BLK_AIUP ASI_BLOCK_AS_IF_USER_PRIMARY
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#define ASI_BLK_AIUPL ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
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#define ASI_BLK_AIUS ASI_BLOCK_AS_IF_USER_SECONDARY
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#define ASI_BLK_AIUSL ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
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#define ASI_BLK_COMMIT_P ASI_BLOCK_COMMIT_PRIMARY
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#define ASI_BLK_COMMIT_PRIMARY ASI_BLOCK_COMMIT_PRIMARY
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#define ASI_BLK_COMMIT_S ASI_BLOCK_COMMIT_SECONDARY
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#define ASI_BLK_COMMIT_SECONDARY ASI_BLOCK_COMMIT_SECONDARY
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#define ASI_BLK_P ASI_BLOCK_PRIMARY
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#define ASI_BLK_PL ASI_BLOCK_PRIMARY_LITTLE
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#define ASI_BLK_S ASI_BLOCK_SECONDARY
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#define ASI_BLK_SL ASI_BLOCK_SECONDARY_LITTLE
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/*
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* The following are 4u control registers
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*/
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/*
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* [4u] MMU and Cache Control Register (MCCR)
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* use ASI = 0x45
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*/
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#define ASI_MCCR 0x45
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#define MCCR 0x00
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/* MCCR Bits and their meanings */
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#define MCCR_DMMU_EN 0x08
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#define MCCR_IMMU_EN 0x04
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#define MCCR_DCACHE_EN 0x02
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#define MCCR_ICACHE_EN 0x01
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/*
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* MMU control registers
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*/
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/* Choose an MMU */
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#define ASI_DMMU 0x58
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#define ASI_IMMU 0x50
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/* Other assorted MMU ASIs */
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#define ASI_IMMU_8KPTR 0x51
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#define ASI_IMMU_64KPTR 0x52
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#define ASI_IMMU_DATA_IN 0x54
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#define ASI_IMMU_TLB_DATA 0x55
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#define ASI_IMMU_TLB_TAG 0x56
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#define ASI_DMMU_8KPTR 0x59
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#define ASI_DMMU_64KPTR 0x5a
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#define ASI_DMMU_DATA_IN 0x5c
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#define ASI_DMMU_TLB_DATA 0x5d
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#define ASI_DMMU_TLB_TAG 0x5e
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/*
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* The following are the control registers
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* They work on both MMUs unless noted.
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*
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* Register contents are defined later on individual registers.
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*/
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#define TSB_TAG_TARGET 0x0
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#define TLB_DATA_IN 0x0
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#define CTX_PRIMARY 0x08 /* primary context -- DMMU only */
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#define CTX_SECONDARY 0x10 /* secondary context -- DMMU only */
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#define SFSR 0x18
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#define SFAR 0x20 /* fault address -- DMMU only */
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#define TSB 0x28
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#define TLB_TAG_ACCESS 0x30
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#define VIRTUAL_WATCHPOINT 0x38
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#define PHYSICAL_WATCHPOINT 0x40
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/* Tag Target bits */
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#define TAG_TARGET_VA_MASK 0x03ffffffffffffffffLL
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#define TAG_TARGET_VA(x) (((x)<<22)&TAG_TARGET_VA_MASK)
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#define TAG_TARGET_CONTEXT(x) ((x)>>48)
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#define TAG_TARGET(c,v) ((((uint64_t)c)<<48)|(((uint64_t)v)&TAG_TARGET_VA_MASK))
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/* SFSR bits for both D_SFSR and I_SFSR */
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#define SFSR_ASI(x) ((x)>>16)
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#define SFSR_FT_VA_OOR_2 0x02000 /* IMMU: jumpl or return to unsupportd VA */
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#define SFSR_FT_VA_OOR_1 0x01000 /* fault at unsupported VA */
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#define SFSR_FT_NFO 0x00800 /* DMMU: Access to page marked NFO */
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#define SFSR_ILL_ASI 0x00400 /* DMMU: Illegal (unsupported) ASI */
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#define SFSR_FT_IO_ATOMIC 0x00200 /* DMMU: Atomic access to noncacheable page */
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#define SFSR_FT_ILL_NF 0x00100 /* DMMU: NF load or flush to page marked E (has side effects) */
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#define SFSR_FT_PRIV 0x00080 /* Privilege violation */
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#define SFSR_FT_E 0x00040 /* DMUU: value of E bit associated address */
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#define SFSR_CTXT(x) (((x)>>4)&0x3)
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#define SFSR_CTXT_IS_PRIM(x) (SFSR_CTXT(x)==0x00)
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#define SFSR_CTXT_IS_SECOND(x) (SFSR_CTXT(x)==0x01)
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#define SFSR_CTXT_IS_NUCLEUS(x) (SFSR_CTXT(x)==0x02)
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#define SFSR_PRIV 0x00008 /* value of PSTATE.PRIV for faulting access */
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#define SFSR_W 0x00004 /* DMMU: attempted write */
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#define SFSR_OW 0x00002 /* Overwrite; prev vault was still valid */
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#define SFSR_FV 0x00001 /* Fault is valid */
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#define SFSR_FT (SFSR_FT_VA_OOR_2|SFSR_FT_VA_OOR_1|SFSR_FT_NFO|SFSR_ILL_ASI|SFSR_FT_IO_ATOMIC|SFSR_FT_ILL_NF|SFSR_FT_PRIV)
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#if 0
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/* Old bits */
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#define SFSR_BITS "\40\16VAT\15VAD\14NFO\13ASI\12A\11NF\10PRIV\7E\6NUCLEUS\5SECONDCTX\4PRIV\3W\2OW\1FV"
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#else
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/* New bits */
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#define SFSR_BITS "\177\20" \
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"f\20\30ASI\0" "b\16VAT\0" "b\15VAD\0" "b\14NFO\0" "b\13ASI\0" "b\12A\0" "b\11NF\0" "b\10PRIV\0" \
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"b\7E\0" "b\6NUCLEUS\0" "b\5SECONDCTX\0" "b\4PRIV\0" "b\3W\0" "b\2OW\0" "b\1FV\0"
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#endif
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/* ASFR bits */
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#define ASFR_ME 0x100000000LL
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#define ASFR_PRIV 0x080000000LL
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#define ASFR_ISAP 0x040000000LL
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#define ASFR_ETP 0x020000000LL
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#define ASFR_IVUE 0x010000000LL
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#define ASFR_TO 0x008000000LL
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#define ASFR_BERR 0x004000000LL
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#define ASFR_LDP 0x002000000LL
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#define ASFR_CP 0x001000000LL
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#define ASFR_WP 0x000800000LL
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#define ASFR_EDP 0x000400000LL
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#define ASFR_UE 0x000200000LL
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#define ASFR_CE 0x000100000LL
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#define ASFR_ETS 0x0000f0000LL
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#define ASFT_P_SYND 0x00000ffffLL
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#define AFSR_BITS "\177\20" \
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"b\40ME\0" "b\37PRIV\0" "b\36ISAP\0" "b\35ETP\0" \
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"b\34IVUE\0" "b\33TO\0" "b\32BERR\0" "b\31LDP\0" \
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"b\30CP\0" "b\27WP\0" "b\26EDP\0" "b\25UE\0" \
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"b\24CE\0" "f\20\4ETS\0" "f\0\20P_SYND\0"
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/*
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* Here's the spitfire TSB control register bits.
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*
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* Each TSB entry is 16-bytes wide. The TSB must be size aligned
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*/
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#define TSB_SIZE_512 0x0 /* 8kB, etc. */
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#define TSB_SIZE_1K 0x01
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#define TSB_SIZE_2K 0x02
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#define TSB_SIZE_4K 0x03
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#define TSB_SIZE_8K 0x04
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#define TSB_SIZE_16K 0x05
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#define TSB_SIZE_32K 0x06
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#define TSB_SIZE_64K 0x07
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#define TSB_SPLIT 0x1000
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#define TSB_BASE 0xffffffffffffe000
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/* TLB Tag Access bits */
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#define TLB_TAG_ACCESS_VA 0xffffffffffffe000
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#define TLB_TAG_ACCESS_CTX 0x0000000000001fff
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/*
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* TLB demap registers. TTEs are defined in v9pte.h
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*
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* Use the address space to select between IMMU and DMMU.
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* The address of the register selects which context register
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* to read the ASI from.
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*
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* The data stored in the register is interpreted as the VA to
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* use. The DEMAP_CTX_<> registers ignore the address and demap the
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* entire ASI.
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*
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*/
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#define ASI_IMMU_DEMAP 0x57 /* [4u] IMMU TLB demap */
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#define ASI_DMMU_DEMAP 0x5f /* [4u] IMMU TLB demap */
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#define DEMAP_PAGE_NUCLEUS ((0x02)<<4) /* Demap page from kernel AS */
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#define DEMAP_PAGE_PRIMARY ((0x00)<<4) /* Demap a page from primary CTXT */
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#define DEMAP_PAGE_SECONDARY ((0x01)<<4) /* Demap page from secondary CTXT (DMMU only) */
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#define DEMAP_CTX_NUCLEUS ((0x06)<<4) /* Demap all of kernel CTXT */
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#define DEMAP_CTX_PRIMARY ((0x04)<<4) /* Demap all of primary CTXT */
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#define DEMAP_CTX_SECONDARY ((0x05)<<4) /* Demap all of secondary CTXT */
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/*
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* Interrupt registers. This really gets hairy.
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*/
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|
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/* IRSR -- Interrupt Receive Status Ragister */
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#define ASI_IRSR 0x49
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#define IRSR 0x00
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#define IRSR_BUSY 0x010
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#define IRSR_MID(x) (x&0xf)
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|
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/* IRDR -- Interrupt Receive Data Registers */
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#define ASI_IRDR 0x7f
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#define IRDR_0H 0x40
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#define IRDR_0L 0x48 /* unimplemented */
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#define IRDR_1H 0x50
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#define IRDR_1L 0x58 /* unimplemented */
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#define IRDR_2H 0x60
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#define IRDR_2L 0x68 /* unimplemented */
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#define IRDR_3H 0x70 /* unimplemented */
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#define IRDR_3L 0x78 /* unimplemented */
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/* SOFTINT ASRs */
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#define SET_SOFTINT %asr20 /* Sets these bits */
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#define CLEAR_SOFTINT %asr21 /* Clears these bits */
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#define SOFTINT %asr22 /* Reads the register */
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#define TICK_INT 0x01 /* level-14 clock tick */
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#define SOFTINT1 (0x1<<1)
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#define SOFTINT2 (0x1<<2)
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#define SOFTINT3 (0x1<<3)
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#define SOFTINT4 (0x1<<4)
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#define SOFTINT5 (0x1<<5)
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#define SOFTINT6 (0x1<<6)
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#define SOFTINT7 (0x1<<7)
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#define SOFTINT8 (0x1<<8)
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#define SOFTINT9 (0x1<<9)
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#define SOFTINT10 (0x1<<10)
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#define SOFTINT11 (0x1<<11)
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#define SOFTINT12 (0x1<<12)
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#define SOFTINT13 (0x1<<13)
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#define SOFTINT14 (0x1<<14)
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#define SOFTINT15 (0x1<<15)
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|
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/* Interrupt Dispatch -- usually reserved for cross-calls */
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|
#define ASR_IDSR 0x48 /* Interrupt dispatch status reg */
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|
#define IDSR 0x00
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#define IDSR_NACK 0x02
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#define IDSR_BUSY 0x01
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|
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#define ASI_INTERRUPT_DISPATCH 0x77 /* [4u] spitfire interrupt dispatch regs */
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#define IDCR(x) (((x)<<14)&0x70) /* Store anything to this address to dispatch crosscall to CPU (x) */
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#define IDDR_0H 0x40 /* Store data to send in these regs */
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|
#define IDDR_0L 0x48 /* unimplemented */
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|
#define IDDR_1H 0x50
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|
#define IDDR_1L 0x58 /* unimplemented */
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|
#define IDDR_2H 0x60
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|
#define IDDR_2L 0x68 /* unimplemented */
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|
#define IDDR_3H 0x70 /* unimplemented */
|
|
#define IDDR_3L 0x78 /* unimplemented */
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|
|
|
/*
|
|
* Error registers
|
|
*/
|
|
|
|
/* Since we won't try to fix async errs, we don't care about the bits in the regs */
|
|
#define ASI_AFAR 0x4d /* Asynchronous fault address register */
|
|
#define AFAR 0x00
|
|
#define ASI_AFSR 0x4c /* Asynchronous fault status register */
|
|
#define AFSR 0x00
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|
|
|
#define ASI_P_EER 0x4b /* Error enable register */
|
|
#define P_EER 0x00
|
|
#define P_EER_ISAPEN 0x04 /* Enable fatal on ISAP */
|
|
#define P_EER_NCEEN 0x02 /* Enable trap on uncorrectable errs */
|
|
#define P_EER_CEEN 0x01 /* Enable trap on correctable errs */
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|
|
|
#define ASI_DATAPATH_READ 0x7f /* Read the regs */
|
|
#define ASI_DATAPATH_WRITE 0x77 /* Write to the regs */
|
|
#define P_DPER_0 0x00 /* Datapath err reg 0 */
|
|
#define P_DPER_1 0x18 /* Datapath err reg 1 */
|
|
#define P_DCR_0 0x20 /* Datapath control reg 0 */
|
|
#define P_DCR_1 0x38 /* Datapath control reg 0 */
|
|
|
|
|
|
/* From sparc64/asm.h which I think I'll deprecate since it makes bus.h a pain. */
|
|
|
|
/*
|
|
* GCC __asm constructs for doing assembly stuff.
|
|
*/
|
|
|
|
/*
|
|
* ``Routines'' to load and store from/to alternate address space.
|
|
* The location can be a variable, the asi value (address space indicator)
|
|
* must be a constant.
|
|
*
|
|
* N.B.: You can put as many special functions here as you like, since
|
|
* they cost no kernel space or time if they are not used.
|
|
*
|
|
* These were static inline functions, but gcc screws up the constraints
|
|
* on the address space identifiers (the "n"umeric value part) because
|
|
* it inlines too late, so we have to use the funny valued-macro syntax.
|
|
*/
|
|
/* load byte from alternate address space */
|
|
#define lduba(loc, asi) ({ \
|
|
register int _lduba_v; \
|
|
__asm __volatile("wr %2,%%g0,%%asi; lduba [%1]%%asi,%0" : "=r" (_lduba_v) : \
|
|
"r" ((long long)(loc)), "r" (asi)); \
|
|
_lduba_v; \
|
|
})
|
|
|
|
/* load half-word from alternate address space */
|
|
#define lduha(loc, asi) ({ \
|
|
register int _lduha_v; \
|
|
__asm __volatile("wr %2,%%g0,%%asi; lduha [%1]%%asi,%0" : "=r" (_lduha_v) : \
|
|
"r" ((long long)(loc)), "r" (asi)); \
|
|
_lduha_v; \
|
|
})
|
|
|
|
/* load int from alternate address space */
|
|
#define lda(loc, asi) ({ \
|
|
register int _lda_v; \
|
|
__asm __volatile("wr %2,%%g0,%%asi; lda [%1]%%asi,%0" : "=r" (_lda_v) : \
|
|
"r" ((int)(loc)), "r" (asi)); \
|
|
_lda_v; \
|
|
})
|
|
|
|
#define ldswa(loc, asi) ({ \
|
|
register int _lda_v; \
|
|
__asm __volatile("wr %2,%%g0,%%asi; ldswa [%1]%%asi,%0" : "=r" (_lda_v) : \
|
|
"r" ((int)(loc)), "r" (asi)); \
|
|
_lda_v; \
|
|
})
|
|
|
|
/* store byte to alternate address space */
|
|
#define stba(loc, asi, value) ({ \
|
|
__asm __volatile("wr %2,%%g0,%%asi; stba %0,[%1]%%asi; membar #Sync" : : \
|
|
"r" ((int)(value)), "r" ((int)(loc)), "r" (asi)); \
|
|
})
|
|
|
|
/* store half-word to alternate address space */
|
|
#define stha(loc, asi, value) ({ \
|
|
__asm __volatile("wr %2,%%g0,%%asi; stha %0,[%1]%%asi; membar #Sync" : : \
|
|
"r" ((int)(value)), "r" ((int)(loc)), "r" (asi)); \
|
|
})
|
|
|
|
/* store int to alternate address space */
|
|
#define sta(loc, asi, value) ({ \
|
|
__asm __volatile("wr %2,%%g0,%%asi; sta %0,[%1]%%asi; membar #Sync" : : \
|
|
"r" ((int)(value)), "r" ((int)(loc)), "r" (asi)); \
|
|
})
|
|
|
|
/* load 64-bit int from alternate address space */
|
|
#define ldda(loc, asi) ({ \
|
|
register long long _lda_v; \
|
|
__asm __volatile("wr %2,%%g0,%%asi; ldda [%1]%%asi,%0" : "=r" (_lda_v) : \
|
|
"r" ((int)(loc)), "r" (asi)); \
|
|
_lda_v; \
|
|
})
|
|
|
|
/* store 64-bit int to alternate address space */
|
|
#define stda(loc, asi, value) ({ \
|
|
__asm __volatile("wr %2,%%g0,%%asi; stda %0,[%1]%%asi; membar #Sync" : : \
|
|
"r" ((long long)(value)), "r" ((int)(loc)), "r" (asi)); \
|
|
})
|
|
|
|
#ifdef _LP64
|
|
/* native load 64-bit int from alternate address space w/64-bit compiler*/
|
|
#define ldxa(loc, asi) ({ \
|
|
register long _lda_v; \
|
|
__asm __volatile("wr %2,%%g0,%%asi; ldxa [%1]%%asi,%0" : "=r" (_lda_v) : \
|
|
"r" ((long)(loc)), "r" (asi)); \
|
|
_lda_v; \
|
|
})
|
|
#else
|
|
/* native load 64-bit int from alternate address space w/32-bit compiler*/
|
|
#define ldxa(loc, asi) ({ \
|
|
volatile register long _ldxa_lo, _ldxa_hi; \
|
|
__asm __volatile("wr %3,%%g0,%%asi; ldxa [%2]%%asi,%0; srlx %0,32,%1; srl %0,0,%0;" : \
|
|
"=r" (_ldxa_lo), "=r" (_ldxa_hi) : \
|
|
"r" ((long)(loc)), "r" (asi)); \
|
|
((((int64_t)_ldxa_hi)<<32)|_ldxa_lo); \
|
|
})
|
|
#endif
|
|
|
|
#ifdef _LP64
|
|
/* native store 64-bit int to alternate address space w/64-bit compiler*/
|
|
#define stxa(loc, asi, value) ({ \
|
|
__asm __volatile("wr %2,%%g0,%%asi; stxa %0,[%1]%%asi; membar #Sync" : : \
|
|
"r" ((long)(value)), "r" ((long)(loc)), "r" (asi)); \
|
|
})
|
|
#else
|
|
/* native store 64-bit int to alternate address space w/32-bit compiler*/
|
|
#define stxa(loc, asi, value) ({ \
|
|
int64_t _stxa_v; \
|
|
int64_t *_stxa_a = &_stxa_v; \
|
|
_stxa_v = value; \
|
|
__asm __volatile("wr %2,%%g0,%%asi; ldx [%0],%3; stxa %3,[%1]%%asi; membar #Sync" : : \
|
|
"r" ((long)(_stxa_a)), "r" ((long)(loc)), "r" (asi), "r" ((long)(_stxa_v))); \
|
|
})
|
|
#endif
|
|
|
|
/* flush address from data cache */
|
|
#define flush(loc) ({ \
|
|
__asm __volatile("flush %0" : : \
|
|
"r" ((long)(loc))); \
|
|
})
|
|
|
|
#define membar_sync() __asm __volatile("membar #Sync" : :)
|
|
|
|
#ifdef _LP64
|
|
/* read 64-bit %tick register */
|
|
#define tick() ({ \
|
|
register u_long _tick_tmp; \
|
|
__asm __volatile("rdpr %%tick, %0" : "=r" (_tick_tmp) :); \
|
|
_tick_tmp; \
|
|
})
|
|
#else
|
|
/* native load 64-bit int from alternate address space w/32-bit compiler*/
|
|
#define tick() ({ \
|
|
volatile register u_long _tick_tmp = 0; \
|
|
volatile u_int64_t _tick_v; \
|
|
volatile u_int64_t *_tick_a = &_tick_v; \
|
|
__asm __volatile("rdpr %%tick, %0; stx %0,[%1]; membar #StoreLoad" : "=r" (_tick_tmp) : \
|
|
"r" ((long)(_tick_a))); \
|
|
_tick_v; \
|
|
})
|
|
#endif
|
|
|