172 lines
6.5 KiB
C
172 lines
6.5 KiB
C
/*
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* Copyright (c) 1994 Timo Rossi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Timo Rossi
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id: if_edreg.h,v 1.1 1994/07/16 02:27:45 chopps Exp $
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*/
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/*
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* The Hydra Systems card uses the National Semiconductor
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* 8390 NIC (Network Interface Controller) chip, located
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* at card base address + 0xffe1. NIC registers are accessible
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* only at odd byte addresses, so the register offsets must
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* be multiplied by two.
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*
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* Card address PROM is located at card base + 0xffc0 (even byte addresses)
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*
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* RAM starts at the card base address, and is 16K or 64K.
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* The current Amiga NetBSD hydra driver is hardwired for 16K.
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* It seems that the RAM should be accessed as words or longwords only.
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*
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*/
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#define HYDRA_NIC_BASE 0xffe1
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/* Page0 registers */
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#define NIC_CR 0 /* Command register */
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#define NIC_PSTART (1*2) /* Page start (write) */
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#define NIC_PSTOP (2*2) /* Page stop (write) */
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#define NIC_BNDRY (3*2) /* Boundary pointer */
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#define NIC_TSR (4*2) /* Transmit status (read) */
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#define NIC_TPSR (4*2) /* Transmit page start (write) */
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#define NIC_NCR (5*2) /* Number of collisions, read */
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#define NIC_TBCR0 (5*2) /* Transmit byte count low (write) */
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#define NIC_FIFO (6*2) /* FIFO reg. (read) */
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#define NIC_TBCR1 (6*2) /* Transmit byte count high (write) */
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#define NIC_ISR (7*2) /* Interrupt status register */
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#define NIC_RBCR0 (0xa*2) /* Remote byte count low (write) */
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#define NIC_RBCR1 (0xb*2) /* Remote byte count high (write) */
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#define NIC_RSR (0xc*2) /* Receive status (read) */
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#define NIC_RCR (0xc*2) /* Receive config (write) */
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#define NIC_CNTR0 (0xd*2) /* Frame alignment error count (read) */
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#define NIC_TCR (0xd*2) /* Transmit config (write) */
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#define NIC_CNTR1 (0xe*2) /* CRC error counter (read) */
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#define NIC_DCR (0xe*2) /* Data config (write) */
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#define NIC_CNTR2 (0xf*2) /* missed packet counter (read) */
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#define NIC_IMR (0xf*2) /* Interrupt mask reg. (write) */
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/* Page1 registers */
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#define NIC_PAR0 (1*2) /* Physical address */
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#define NIC_PAR1 (2*2)
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#define NIC_PAR2 (3*2)
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#define NIC_PAR3 (4*2)
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#define NIC_PAR4 (5*2)
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#define NIC_PAR5 (6*2)
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#define NIC_CURR (7*2) /* Current RX ring-buffer page */
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#define NIC_MAR0 (8*2) /* Multicast address */
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#define NIC_MAR1 (9*2)
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#define NIC_MAR2 (0xa*2)
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#define NIC_MAR3 (0xb*2)
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#define NIC_MAR4 (0xc*2)
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#define NIC_MAR5 (0xd*2)
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#define NIC_MAR6 (0xe*2)
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#define NIC_MAR7 (0xf*2)
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/* Command register definitions */
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#define CR_STOP 0x01 /* Stop -- software reset command */
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#define CR_START 0x02 /* Start */
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#define CR_TXP 0x04 /* Transmit packet */
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#define CR_RD0 0x08 /* Remote DMA cmd */
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#define CR_RD1 0x10
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#define CR_RD2 0x20
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#define CR_NODMA CR_RD2
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#define CR_PS0 0x40 /* Page select */
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#define CR_PS1 0x80
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#define CR_PAGE0 0
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#define CR_PAGE1 CR_PS0
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#define CR_PAGE2 CR_PS1
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/* Interrupt status reg. definitions */
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#define ISR_PRX 0x01 /* Packet received without errors */
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#define ISR_PTX 0x02 /* Packet transmitted without errors */
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#define ISR_RXE 0x04 /* Receive error */
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#define ISR_TXE 0x08 /* Transmit error */
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#define ISR_OVW 0x10 /* Ring buffer overrrun */
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#define ISR_CNT 0x20 /* Counter overflow */
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#define ISR_RDC 0x40 /* Remote DMA compile */
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#define ISR_RST 0x80 /* Reset status */
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/* Data config reg. definitions */
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#define DCR_WTS 0x01 /* Word transfer select */
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#define DCR_BOS 0x02 /* Byte order select */
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#define DCR_LAS 0x04 /* Long address select */
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#define DCR_LS 0x08 /* Loopback select */
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#define DCR_AR 0x10 /* Auto-init remote */
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#define DCR_FT0 0x20 /* FIFO threshold select */
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#define DCR_FT1 0x40
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/* Transmit config reg. definitions */
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#define TCR_CRC 0x01 /* Inhibit CRC */
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#define TCR_LB0 0x02 /* Loopback control */
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#define TCR_LB1 0x04
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#define TCR_ATD 0x08 /* Auto transmit disable */
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#define TCR_OFST 0x10 /* Collision offset enable */
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/* Transmit status reg. definitions */
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#define TSR_PTX 0x01 /* Packet transmitted */
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#define TSR_COL 0x04 /* Transmit collided */
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#define TSR_ABT 0x08 /* Transmit aborted */
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#define TSR_CRS 0x10 /* Carrier sense lost */
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#define TSR_FU 0x20 /* FIFO underrun */
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#define TSR_CDH 0x40 /* CD Heartbeat */
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#define TSR_OWC 0x80 /* Out of Window Collision */
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/* Receiver config register definitions */
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#define RCR_SEP 0x01 /* Save errored packets */
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#define RCR_AR 0x02 /* Accept runt packets */
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#define RCR_AB 0x04 /* Accept broadcast */
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#define RCR_AM 0x08 /* Accept multicast */
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#define RCR_PRO 0x10 /* Promiscuous mode */
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#define RCR_MON 0x20 /* Monitor mode */
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/* Receiver status register definitions */
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#define RSR_PRX 0x01 /* Packet received without error */
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#define RSR_CRC 0x02 /* CRC error */
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#define RSR_FAE 0x04 /* Frame alignment error */
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#define RSR_FO 0x08 /* FIFO overrun */
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#define RSR_MPA 0x10 /* Missed packet */
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#define RSR_PHY 0x20 /* Physical address */
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#define RSR_DIS 0x40 /* Received disabled */
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#define RSR_DFR 0x80 /* Deferring (jabber) */
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/* Hydra System card address PROM offset */
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#define HYDRA_ADDRPROM 0xffc0
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