299 lines
8.5 KiB
C
299 lines
8.5 KiB
C
/* $NetBSD: mcp23xxxgpio_spi.c,v 1.4 2022/01/19 05:21:44 thorpej Exp $ */
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/*-
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* Copyright (c) 2014, 2022 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Frank Kardel, and by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: mcp23xxxgpio_spi.c,v 1.4 2022/01/19 05:21:44 thorpej Exp $");
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/*
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* Driver for Microchip serial I/O expanders:
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*
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* MCP23S08 8-bit, SPI interface
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* MCP23S17 16-bit, SPI interface
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* MCP23S18 16-bit (open-drain outputs), SPI interface
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*
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* Data sheet:
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*
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* https://ww1.microchip.com/downloads/en/DeviceDoc/20001952C.pdf
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*/
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#include <sys/types.h>
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#include <sys/bitops.h>
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#include <sys/device.h>
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#include <sys/kernel.h>
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#include <sys/mutex.h>
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#include <dev/ic/mcp23xxxgpioreg.h>
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#include <dev/ic/mcp23xxxgpiovar.h>
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#include <dev/spi/spivar.h>
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/*
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* Multi-chip-on-select configurations appear to the upper layers like
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* additional GPIO banks; mixing different chip types on the same chip
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* select is not allowed.
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*
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* Some chips have 2 banks per chip, and we have up to 8 chips per chip
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* select, it's a total of 16 banks per chip select / driver instance.
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*/
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#define MCPGPIO_SPI_MAXBANKS 16
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struct mcpgpio_spi_softc {
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struct mcpgpio_softc sc_mcpgpio;
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kmutex_t sc_mutex;
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struct spi_handle *sc_sh;
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uint8_t sc_ha[MCPGPIO_SPI_MAXBANKS];
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};
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/*
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* SPI-specific commands (the serial interface on the I2C flavor of
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* the chip uses the I2C protocol to infer this information). Careful
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* readers will note that this ends up being exactly the same bits
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* on the serial interface that the I2C flavor of the chip uses.
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*
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* The SPI version can have up to 4 (or 8) chips per chip-select, demuxed
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* using the hardware address (selected by tying the 2 or 3 HA pins high/low
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* as desired).
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*/
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#define OP_READ(ha) (0x41 | ((ha) << 1))
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#define OP_WRITE(ha) (0x40 | ((ha) << 1))
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#define MCPGPIO_TO_SPI(sc) \
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container_of((sc), struct mcpgpio_spi_softc, sc_mcpgpio)
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#if 0
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static const struct mcpgpio_variant mcp23s08 = {
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.name = "MCP23S08",
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.type = MCPGPIO_TYPE_23x08,
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};
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#endif
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static const struct mcpgpio_variant mcp23s17 = {
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.name = "MCP23S17",
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.type = MCPGPIO_TYPE_23x17,
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};
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#if 0
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static const struct mcpgpio_variant mcp23s18 = {
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.name = "MCP23S18",
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.type = MCPGPIO_TYPE_23x18,
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};
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#endif
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#if 0
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static const struct device_compatible_entry compat_data[] = {
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{ .compat = "microchip,mcp23s08", .data = &mcp23s08 },
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{ .compat = "microchip,mcp23s17", .data = &mcp23s17 },
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{ .compat = "microchip,mcp23s18", .data = &mcp23s18 },
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DEVICE_COMPAT_EOL
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};
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#endif
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static int
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mcpgpio_spi_lock(struct mcpgpio_softc *sc)
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{
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struct mcpgpio_spi_softc *ssc = MCPGPIO_TO_SPI(sc);
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mutex_enter(&ssc->sc_mutex);
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return 0;
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}
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static void
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mcpgpio_spi_unlock(struct mcpgpio_softc *sc)
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{
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struct mcpgpio_spi_softc *ssc = MCPGPIO_TO_SPI(sc);
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mutex_exit(&ssc->sc_mutex);
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}
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static int
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mcpgpio_spi_read(struct mcpgpio_softc *sc, unsigned int bank,
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uint8_t reg, uint8_t *valp)
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{
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struct mcpgpio_spi_softc *ssc = MCPGPIO_TO_SPI(sc);
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uint8_t buf[2];
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KASSERT(bank < (sc->sc_npins >> 3));
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buf[0] = OP_READ(ssc->sc_ha[bank]);
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buf[1] = reg;
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return spi_send_recv(ssc->sc_sh, 2, buf, 1, valp);
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}
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static int
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mcpgpio_spi_write(struct mcpgpio_softc *sc, unsigned int bank,
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uint8_t reg, uint8_t val)
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{
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struct mcpgpio_spi_softc *ssc = MCPGPIO_TO_SPI(sc);
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uint8_t buf[3];
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KASSERT(bank < (sc->sc_npins >> 3));
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buf[0] = OP_WRITE(ssc->sc_ha[bank]);
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buf[1] = reg;
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buf[2] = val;
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return spi_send(ssc->sc_sh, 3, buf);
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}
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static const struct mcpgpio_accessops mcpgpio_spi_accessops = {
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.lock = mcpgpio_spi_lock,
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.unlock = mcpgpio_spi_unlock,
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.read = mcpgpio_spi_read,
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.write = mcpgpio_spi_write,
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};
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static int
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mcpgpio_spi_match(device_t parent, cfdata_t cf, void *aux)
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{
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/* MCP23S17 has no way to detect it! */
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return 1;
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}
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static void
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mcpgpio_spi_attach(device_t parent, device_t self, void *aux)
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{
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struct mcpgpio_spi_softc *ssc = device_private(self);
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struct mcpgpio_softc *sc = &ssc->sc_mcpgpio;
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struct spi_attach_args *sa = aux;
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uint32_t spi_present_mask;
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int bank, nchips, error, ha;
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mutex_init(&ssc->sc_mutex, MUTEX_DEFAULT, IPL_NONE);
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ssc->sc_sh = sa->sa_handle;
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sc->sc_dev = self;
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sc->sc_variant = &mcp23s17; /* XXX */
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sc->sc_iocon = IOCON_HAEN | IOCON_SEQOP;
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sc->sc_npins = MCP23x17_GPIO_NPINS;
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sc->sc_accessops = &mcpgpio_spi_accessops;
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aprint_naive("\n");
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aprint_normal(": %s I/O Expander\n", sc->sc_variant->name);
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/* run at 10MHz */
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error = spi_configure(self, sa->sa_handle, SPI_MODE_0, 10000000);
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if (error) {
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return;
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}
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/*
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* Before we decode the topology information, ensure each
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* chip has IOCON.HAEN set so that it will actually decode
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* the address bits.
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*
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* XXX Going on blind faith that IOCON.BANK is already 0.
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*/
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if (sc->sc_variant->type == MCPGPIO_TYPE_23x08) {
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error = mcpgpio_spi_write(sc, 0, REG_IOCON, sc->sc_iocon);
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} else {
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error = mcpgpio_spi_write(sc, 0, REGADDR_BANK0(0, REG_IOCON),
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sc->sc_iocon);
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if (error == 0) {
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error = mcpgpio_spi_write(sc, 1,
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REGADDR_BANK0(1, REG_IOCON), sc->sc_iocon);
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}
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}
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if (error) {
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aprint_error_dev(self,
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"unable to initialize IOCON, error=%d\n", error);
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return;
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}
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#if 0
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/*
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* The number of devices sharing this chip select, along
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* with their assigned addresses, is encoded in the
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* "microchip,spi-present-mask" property. Note that this
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* device tree binding means that we will just have a
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* single driver instance for however many chips are on
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* this chip select. We treat them logically as banks.
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*/
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if (of_getprop_uint32(phandle, "microchip,spi-present-mask",
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&spi_present_mask) != 0 ||
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of_getprop_uint32(phandle, "mcp,spi-present-mask",
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&spi_present_mask) != 0) {
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aprint_error_dev(self,
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"missing \"microchip,spi-present-mask\" property\n");
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return false;
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}
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#else
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/*
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* XXX Until we support decoding the DT properties that
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* XXX give us the topology information.
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*/
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spi_present_mask = __BIT(device_cfdata(self)->cf_flags & 0x7);
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#endif
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/*
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* The 23S08 has 2 address pins (4 devices per chip select),
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* and the others have 3 (8 devices per chip select).
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*/
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if (spi_present_mask == 0 ||
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(sc->sc_variant->type == MCPGPIO_TYPE_23x08 &&
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spi_present_mask >= __BIT(4)) ||
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(sc->sc_variant->type != MCPGPIO_TYPE_23x08 &&
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spi_present_mask >= __BIT(8))) {
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aprint_error_dev(self,
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"invalid \"microchip,spi-present-mask\" value: 0x%08x\n",
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spi_present_mask);
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return;
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}
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nchips = popcount32(spi_present_mask);
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sc->sc_npins = nchips *
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(sc->sc_variant->type == MCPGPIO_TYPE_23x08 ? MCP23x08_GPIO_NPINS
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: MCP23x17_GPIO_NPINS);
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/* Record the hardware addresses for each logical bank of 8 pins. */
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for (bank = 0; spi_present_mask != 0; spi_present_mask &= ~__BIT(ha)) {
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int ha_first, ha_last;
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ha = ffs32(spi_present_mask) - 1;
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ha_first = bank * MCPGPIO_PINS_PER_BANK;
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ssc->sc_ha[bank++] = ha;
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if (sc->sc_variant->type != MCPGPIO_TYPE_23x08) {
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ssc->sc_ha[bank++] = ha;
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}
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ha_last = (bank * MCPGPIO_PINS_PER_BANK) - 1;
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aprint_verbose_dev(self, "pins %d..%d at HA %d\n",
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ha_first, ha_last, ha);
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}
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KASSERT((bank * MCPGPIO_PINS_PER_BANK) == sc->sc_npins);
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mcpgpio_attach(sc);
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}
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CFATTACH_DECL_NEW(mcpgpio_spi, sizeof(struct mcpgpio_spi_softc),
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mcpgpio_spi_match, mcpgpio_spi_attach, NULL, NULL);
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