278 lines
9.3 KiB
C
278 lines
9.3 KiB
C
/* $NetBSD: acpi_cpu.h,v 1.42 2011/06/22 08:49:54 jruoho Exp $ */
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/*-
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* Copyright (c) 2010, 2011 Jukka Ruohonen <jruohonen@iki.fi>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _SYS_DEV_ACPI_ACPI_CPU_H
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#define _SYS_DEV_ACPI_ACPI_CPU_H
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/*
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* The following _PDC values are based on:
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*
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* Intel Corporation: Intel Processor-Specific ACPI
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* Interface Specification, September 2006, Revision 005.
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*/
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#define ACPICPU_PDC_REVID 0x1
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#define ACPICPU_PDC_SMP 0xA
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#define ACPICPU_PDC_MSR 0x1
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#define ACPICPU_PDC_P_FFH __BIT(0) /* SpeedStep MSRs */
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#define ACPICPU_PDC_C_C1_HALT __BIT(1) /* C1 "I/O then halt" */
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#define ACPICPU_PDC_T_FFH __BIT(2) /* OnDemand throttling MSRs */
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#define ACPICPU_PDC_C_C1PT __BIT(3) /* SMP C1, Px, and Tx (same) */
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#define ACPICPU_PDC_C_C2C3 __BIT(4) /* SMP C2 and C3 (same) */
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#define ACPICPU_PDC_P_SW __BIT(5) /* SMP Px (different) */
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#define ACPICPU_PDC_C_SW __BIT(6) /* SMP Cx (different) */
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#define ACPICPU_PDC_T_SW __BIT(7) /* SMP Tx (different) */
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#define ACPICPU_PDC_C_C1_FFH __BIT(8) /* SMP C1 native beyond halt */
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#define ACPICPU_PDC_C_C2C3_FFH __BIT(9) /* SMP C2 and C2 native */
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#define ACPICPU_PDC_P_HWF __BIT(11) /* Px hardware feedback */
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#define ACPICPU_PDC_GAS_HW __BIT(0) /* HW-coordinated state */
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#define ACPICPU_PDC_GAS_BM __BIT(1) /* Bus master check required */
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/*
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* Notify values.
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*/
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#define ACPICPU_P_NOTIFY 0x80 /* _PPC */
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#define ACPICPU_C_NOTIFY 0x81 /* _CST */
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#define ACPICPU_T_NOTIFY 0x82 /* _TPC */
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/*
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* Dependency coordination.
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*/
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#define ACPICPU_DEP_SW_ALL 0xFC /* All CPUs must set a state */
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#define ACPICPU_DEP_SW_ANY 0xFD /* Any CPU can set a state */
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#define ACPICPU_DEP_HW_ALL 0xFE /* HW does the coordination */
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/*
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* C-states.
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*/
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#define ACPICPU_C_C2_LATENCY_MAX 100 /* us */
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#define ACPICPU_C_C3_LATENCY_MAX 1000 /* us */
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#define ACPICPU_C_STATE_HALT 0x01
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#define ACPICPU_C_STATE_FFH 0x02
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#define ACPICPU_C_STATE_SYSIO 0x03
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/*
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* P-states.
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*/
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#define ACPICPU_P_STATE_MAX 255 /* Arbitrary upper limit */
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#define ACPICPU_P_STATE_RETRY 100
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#define ACPICPU_P_STATE_UNKNOWN 0x0
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/*
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* T-states.
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*/
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#define ACPICPU_T_STATE_MAX 0x8
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#define ACPICPU_T_STATE_RETRY 0xA
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#define ACPICPU_T_STATE_UNKNOWN 255
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/*
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* Flags.
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*/
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#define ACPICPU_FLAG_C __BIT(0) /* C-states supported */
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#define ACPICPU_FLAG_P __BIT(1) /* P-states supported */
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#define ACPICPU_FLAG_T __BIT(2) /* T-states supported */
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#define ACPICPU_FLAG_PIIX4 __BIT(3) /* Broken (quirk) */
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#define ACPICPU_FLAG_C_FFH __BIT(4) /* Native C-states */
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#define ACPICPU_FLAG_C_FADT __BIT(5) /* C-states with FADT */
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#define ACPICPU_FLAG_C_DEP __BIT(6) /* C-state CPU coordination */
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#define ACPICPU_FLAG_C_BM __BIT(7) /* Bus master control */
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#define ACPICPU_FLAG_C_BM_STS __BIT(8) /* Bus master check required */
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#define ACPICPU_FLAG_C_ARB __BIT(9) /* Bus master arbitration */
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#define ACPICPU_FLAG_C_TSC __BIT(10) /* TSC broken, > C1, Px, Tx */
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#define ACPICPU_FLAG_C_APIC __BIT(11) /* APIC timer broken, > C1 */
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#define ACPICPU_FLAG_C_C1E __BIT(12) /* AMD C1E detected */
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#define ACPICPU_FLAG_P_FFH __BIT(13) /* Native P-states */
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#define ACPICPU_FLAG_P_DEP __BIT(14) /* P-state CPU coordination */
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#define ACPICPU_FLAG_P_HWF __BIT(15) /* HW feedback supported */
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#define ACPICPU_FLAG_P_XPSS __BIT(16) /* Microsoft XPSS in use */
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#define ACPICPU_FLAG_P_TURBO __BIT(17) /* Turbo Boost / Turbo Core */
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#define ACPICPU_FLAG_P_FIDVID __BIT(18) /* AMD "FID/VID algorithm" */
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#define ACPICPU_FLAG_T_FFH __BIT(19) /* Native throttling */
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#define ACPICPU_FLAG_T_FADT __BIT(20) /* Throttling with FADT */
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#define ACPICPU_FLAG_T_DEP __BIT(21) /* T-state CPU coordination */
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/*
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* This is AML_RESOURCE_GENERIC_REGISTER,
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* included here separately for convenience.
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*/
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struct acpicpu_reg {
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uint8_t reg_desc;
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uint16_t reg_reslen;
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uint8_t reg_spaceid;
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uint8_t reg_bitwidth;
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uint8_t reg_bitoffset;
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uint8_t reg_accesssize;
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uint64_t reg_addr;
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} __packed;
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struct acpicpu_dep {
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uint32_t dep_domain;
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uint32_t dep_type;
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uint32_t dep_ncpus;
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uint32_t dep_index;
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};
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struct acpicpu_cstate {
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struct evcnt cs_evcnt;
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char cs_name[EVCNT_STRING_MAX];
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uint64_t cs_addr;
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uint32_t cs_power;
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uint32_t cs_latency;
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int cs_method;
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int cs_flags;
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};
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/*
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* This structure supports both the conventional _PSS and the
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* so-called extended _PSS (XPSS). For the latter, refer to:
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*
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* Microsoft Corporation: Extended PSS ACPI
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* Method Specification, April 2, 2007.
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*/
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struct acpicpu_pstate {
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struct evcnt ps_evcnt;
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char ps_name[EVCNT_STRING_MAX];
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uint32_t ps_freq;
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uint32_t ps_power;
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uint32_t ps_latency;
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uint32_t ps_latency_bm;
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uint64_t ps_control;
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uint64_t ps_control_addr;
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uint64_t ps_control_mask;
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uint64_t ps_status;
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uint64_t ps_status_addr;
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uint64_t ps_status_mask;
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int ps_flags;
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};
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struct acpicpu_tstate {
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struct evcnt ts_evcnt;
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char ts_name[EVCNT_STRING_MAX];
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uint32_t ts_percent;
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uint32_t ts_power;
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uint32_t ts_latency;
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uint32_t ts_control;
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uint32_t ts_status;
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};
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struct acpicpu_object {
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uint32_t ao_procid;
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uint32_t ao_pblklen;
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uint32_t ao_pblkaddr;
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};
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struct acpicpu_softc {
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device_t sc_dev;
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struct cpu_info *sc_ci;
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struct acpi_devnode *sc_node;
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struct acpicpu_object sc_object;
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struct acpicpu_cstate sc_cstate[ACPI_C_STATE_COUNT];
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struct acpicpu_dep sc_cstate_dep;
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uint32_t sc_cstate_sleep;
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struct acpicpu_pstate *sc_pstate;
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struct acpicpu_dep sc_pstate_dep;
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struct acpicpu_reg sc_pstate_control;
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struct acpicpu_reg sc_pstate_status;
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uint64_t sc_pstate_aperf; /* ACPICPU_FLAG_P_HW */
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uint64_t sc_pstate_mperf; /* ACPICPU_FLAG_P_HW*/
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uint32_t sc_pstate_current;
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uint32_t sc_pstate_saved;
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uint32_t sc_pstate_count;
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uint32_t sc_pstate_max;
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uint32_t sc_pstate_min;
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struct acpicpu_tstate *sc_tstate;
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struct acpicpu_dep sc_tstate_dep;
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struct acpicpu_reg sc_tstate_control;
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struct acpicpu_reg sc_tstate_status;
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uint32_t sc_tstate_current;
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uint32_t sc_tstate_count;
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uint32_t sc_tstate_max;
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uint32_t sc_tstate_min;
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kmutex_t sc_mtx;
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uint32_t sc_cap;
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uint32_t sc_ncpus;
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uint32_t sc_flags;
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bool sc_cold;
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};
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void acpicpu_cstate_attach(device_t);
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void acpicpu_cstate_detach(device_t);
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void acpicpu_cstate_start(device_t);
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void acpicpu_cstate_suspend(void *);
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void acpicpu_cstate_resume(void *);
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void acpicpu_cstate_callback(void *);
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void acpicpu_cstate_idle(void);
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void acpicpu_pstate_attach(device_t);
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void acpicpu_pstate_detach(device_t);
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void acpicpu_pstate_start(device_t);
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void acpicpu_pstate_suspend(void *);
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void acpicpu_pstate_resume(void *);
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void acpicpu_pstate_callback(void *);
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int acpicpu_pstate_get(struct cpu_info *, uint32_t *);
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void acpicpu_pstate_set(struct cpu_info *, uint32_t);
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void acpicpu_tstate_attach(device_t);
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void acpicpu_tstate_detach(device_t);
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void acpicpu_tstate_start(device_t);
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void acpicpu_tstate_suspend(void *);
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void acpicpu_tstate_resume(void *);
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void acpicpu_tstate_callback(void *);
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int acpicpu_tstate_get(struct cpu_info *, uint32_t *);
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void acpicpu_tstate_set(struct cpu_info *, uint32_t);
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struct cpu_info *acpicpu_md_match(device_t, cfdata_t, void *);
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struct cpu_info *acpicpu_md_attach(device_t, device_t, void *);
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uint32_t acpicpu_md_flags(void);
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void acpicpu_md_quirk_c1e(void);
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int acpicpu_md_cstate_start(struct acpicpu_softc *);
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int acpicpu_md_cstate_stop(void);
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void acpicpu_md_cstate_enter(int, int);
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int acpicpu_md_pstate_start(struct acpicpu_softc *);
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int acpicpu_md_pstate_stop(void);
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int acpicpu_md_pstate_init(struct acpicpu_softc *);
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uint8_t acpicpu_md_pstate_hwf(struct cpu_info *);
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int acpicpu_md_pstate_get(struct acpicpu_softc *, uint32_t *);
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int acpicpu_md_pstate_set(struct acpicpu_pstate *);
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int acpicpu_md_tstate_get(struct acpicpu_softc *, uint32_t *);
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int acpicpu_md_tstate_set(struct acpicpu_tstate *);
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#endif /* !_SYS_DEV_ACPI_ACPI_CPU_H */
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