206 lines
5.5 KiB
ArmAsm
206 lines
5.5 KiB
ArmAsm
/* $NetBSD: intmmu.S,v 1.11 2011/01/31 06:28:03 matt Exp $ */
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/*
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* Copyright (c) 2001 ARM Ltd
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the company may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <machine/asm.h>
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#include <arm/armreg.h>
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#include "assym.h"
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.section .start,"ax",%progbits
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ASENTRY_NP(integrator_start)
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mov r6, #0x16000000 /* UART0 Physical base*/
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#ifdef VERBOSE_INIT_ARM
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mov r3, #'A'
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str r3, [r6] /* Let the world know we are alive */
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#endif
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/*
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* Check that the processor has a CP15. Some core modules do not.
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* We can tell by reading CM_PROC. If it is zero, then we're OK, otherwise
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* let the user know why we've died.
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*/
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mov r7, #0x10000000
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ldr r3, [r7, #4]
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cmp r3, #0
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bne Lno_cp15
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/*
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* Now read CP15 and check what sort of core we have. We need to know
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* if it has an MMU. There's no simple test for this, but the following
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* hack should be sufficient for all currently supported CM boards:
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* - Check that the product code has a '2' or '3' in bits 8-11
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*/
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mrc p15, 0, r3, c0, c0, 0
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and r0, r3, #0x00000f00
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teq r0, #0x00000200 /* ARM 920, 1020, 1026, etc */
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teqne r0, #0x00000300 /* ARM 1136 */
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bne Lno_mmu
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/*
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* At this time the MMU is off.
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* We build up an initial memory map at 0x8000 that we can use to get
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* the kernel running from the top of memory. All mappings in this table
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* use L1 section maps.
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*/
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/*
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* Set Virtual == Physical
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*/
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mov r3, #(L1_S_AP_KRW)
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add r3, r3, #(L1_TYPE_S)
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mov r2, #0x100000 /* advance by 1MB */
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mov r1, #0x8000 /* page table start */
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mov r0, #0x1000 /* page table size */
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Lflat:
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str r3, [r1], #0x0004
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add r3, r3, r2
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subs r0, r0, #1
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bgt Lflat
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/*
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* Map VA 0xc0000000->0xc03fffff to PA 0x00000000->0x003fffff
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*/
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mov r3, #(L1_S_AP_KRW)
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add r3, r3, #(L1_TYPE_S)
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mov r1, #0x8000 /* page table start */
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add r1, r1, #(0xc00 * 4) /* offset to 0xc00xxxxx */
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# add r1, r1, #(0x001 * 4) /* offset to 0xc01xxxxx */
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mov r0, #63
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Lkern:
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str r3, [r1], #0x0004 /* 0xc000000-0xc03fffff */
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add r3, r3, r2
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subs r0, r0, #1
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bgt Lkern
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/*
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* Mapping the peripheral register region (0x10000000->0x1fffffff) linearly
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* would require 256MB of virtual memory (as much space as the entire kernel
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* virtual space). So we map the first 1M of each 16MB sub-space into the
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* region VA 0xfd000000->0xfdffffff; this should map enough of the peripheral
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* space to at least get us up and running.
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*/
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mov r3, #(L1_S_AP_KRW)
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add r3, r3, #L1_TYPE_S
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add r3, r3, #0x10000000 /* Peripherals base */
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mov r1, #0x8000 /* page table start */
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add r1, r1, #(0xfd0 * 4)
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mov r2, #0x01000000 /* 16MB increment. */
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mov r0, #16
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Lperiph:
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str r3, [r1], #4 /* 0xfd000000-0xfdffffff */
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add r3, r3, r2
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subs r0, r0, #1
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bgt Lperiph
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/*
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* We now have our page table ready, so load it up and light the blue
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* touch paper.
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*/
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/* set the location of the L1 page table */
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mov r1, #0x8000
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mcr p15, 0, r1, c2, c0, 0
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/* Flush the old TLBs (just in case) */
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mcr p15, 0, r1, c8, c7, 0
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/* And the caches */
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mov r0, #0
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mcr p15, 0, r1, c7, c6, 0
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#ifdef VERBOSE_INIT_ARM
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mov r2, #'B'
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strb r2, [r6]
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#endif
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/* Set the Domain Access register. Very important! */
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mov r1, #1
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mcr p15, 0, r1, c3, c0, 0
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/*
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* set mmu bit (don't set anything else for now, we don't know
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* what sort of CPU we have yet.
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*/
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mov r1, #CPU_CONTROL_MMU_ENABLE
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/*
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* This is where it might all start to go wrong if the CPU fitted to your
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* integrator does not have an MMU.
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*/
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/* fetch current control state */
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mrc p15, 0, r2, c1, c0, 0
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orr r2, r2, r1
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/* set new control state */
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mcr p15, 0, r2, c1, c0, 0
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mov r0, r0
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mov r0, r0
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mov r0, r0
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#ifdef VERBOSE_INIT_ARM
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/* emit a char. Uart is now at 0xfd600000 */
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mov r6, #0xfd000000
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add r6, r6, #0x00600000
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mov r2, #'C'
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strb r2, [r6]
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#endif
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/* jump to kernel space */
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mov r0, #0x0200
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/* Switch to kernel VM and really set the ball rolling. */
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ldr pc, Lstart
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Lstart: .long start
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Lmsg:
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ldrb r2, [r0], #1
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cmp r2, #0
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strneb r2, [r6]
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Lwait:
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ldrb r3, [r6, #0x18]
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tst r3, #0x80
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beq Lwait
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cmp r2, #0
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bne Lmsg
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/* We're toast! */
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b .
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Lno_cp15:
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adr r0, Lcp15msg
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b Lmsg
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Lno_mmu:
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adr r0, Lmmumsg
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b Lmsg
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Lcp15msg:
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.ascii "Core has no cp15\r\n\0"
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Lmmumsg:
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.ascii "Core has no MMU\r\n\0"
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