573 lines
16 KiB
C
573 lines
16 KiB
C
/* $NetBSD: isabus.c,v 1.30 2005/11/15 15:07:36 tsutsui Exp $ */
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/* $OpenBSD: isabus.c,v 1.15 1998/03/16 09:38:46 pefo Exp $ */
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/* NetBSD: isa.c,v 1.33 1995/06/28 04:30:51 cgd Exp */
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/*-
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz and Don Ahn.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)isa.c 7.2 (Berkeley) 5/12/91
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*/
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/*-
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* Copyright (c) 1995 Per Fogelstrom
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* Copyright (c) 1993, 1994 Charles M. Hannum.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz and Don Ahn.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)isa.c 7.2 (Berkeley) 5/12/91
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*/
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/*
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* Mach Operating System
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* Copyright (c) 1991,1990,1989 Carnegie Mellon University
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* All Rights Reserved.
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*
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* Permission to use, copy, modify and distribute this software and its
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* documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
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* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie Mellon
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* the rights to redistribute these changes.
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*/
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/*
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Copyright 1988, 1989 by Intel Corporation, Santa Clara, California.
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All Rights Reserved
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Permission to use, copy, modify, and distribute this software and
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its documentation for any purpose and without fee is hereby
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granted, provided that the above copyright notice appears in all
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copies and that both the copyright notice and this permission notice
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appear in supporting documentation, and that the name of Intel
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not be used in advertising or publicity pertaining to distribution
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of the software without specific, written prior permission.
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INTEL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE
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INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS,
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IN NO EVENT SHALL INTEL BE LIABLE FOR ANY SPECIAL, INDIRECT, OR
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CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
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LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT,
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NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION
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WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: isabus.c,v 1.30 2005/11/15 15:07:36 tsutsui Exp $");
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#include <sys/param.h>
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#include <sys/proc.h>
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#include <sys/user.h>
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#include <sys/systm.h>
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#include <sys/callout.h>
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#include <sys/time.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <sys/extent.h>
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#include <uvm/uvm_extern.h>
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#include <machine/cpu.h>
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#include <machine/pio.h>
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#include <machine/autoconf.h>
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#include <machine/intr.h>
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#include <mips/locore.h>
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#include <dev/ic/i8253reg.h>
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#include <dev/isa/isareg.h>
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#include <dev/isa/isavar.h>
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#include <arc/isa/isabrvar.h>
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#include <arc/isa/spkrreg.h>
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#include <arc/arc/timervar.h>
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static int beeping;
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static struct callout sysbeep_ch = CALLOUT_INITIALIZER;
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static long isa_mem_ex_storage[EXTENT_FIXED_STORAGE_SIZE(16) / sizeof(long)];
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static long isa_io_ex_storage[EXTENT_FIXED_STORAGE_SIZE(16) / sizeof(long)];
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#define IRQ_SLAVE 2
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/* Definition of the driver for autoconfig. */
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int isabrprint(void *, const char *);
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extern struct arc_bus_space arc_bus_io, arc_bus_mem;
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void isabr_attach_hook(struct device *, struct device *,
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struct isabus_attach_args *);
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const struct evcnt *isabr_intr_evcnt(isa_chipset_tag_t, int);
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void *isabr_intr_establish(isa_chipset_tag_t, int, int, int,
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int (*)(void *), void *);
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void isabr_intr_disestablish(isa_chipset_tag_t, void*);
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uint32_t isabr_iointr(uint32_t, struct clockframe *);
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void isabr_initicu(void);
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void intr_calculatemasks(void);
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int fakeintr(void *a);
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struct isabr_config *isabr_conf = NULL;
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uint32_t imask[_IPL_N]; /* XXX */
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void
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isabrattach(struct isabr_softc *sc)
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{
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struct isabus_attach_args iba;
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if (isabr_conf == NULL)
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panic("isabr_conf isn't initialized");
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printf("\n");
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/* Initialize interrupt controller */
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isabr_initicu();
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/*XXX we may remove the abus part of the softc struct... */
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sc->sc_bus.ab_dv = (struct device *)sc;
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sc->sc_bus.ab_type = BUS_ISABR;
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sc->arc_isa_cs.ic_attach_hook = isabr_attach_hook;
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sc->arc_isa_cs.ic_intr_evcnt = isabr_intr_evcnt;
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sc->arc_isa_cs.ic_intr_establish = isabr_intr_establish;
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sc->arc_isa_cs.ic_intr_disestablish = isabr_intr_disestablish;
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arc_bus_space_init_extent(&arc_bus_mem, (caddr_t)isa_mem_ex_storage,
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sizeof(isa_mem_ex_storage));
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arc_bus_space_init_extent(&arc_bus_io, (caddr_t)isa_io_ex_storage,
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sizeof(isa_io_ex_storage));
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iba.iba_iot = &arc_bus_io;
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iba.iba_memt = &arc_bus_mem;
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iba.iba_dmat = &sc->sc_dmat;
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iba.iba_ic = &sc->arc_isa_cs;
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config_found_ia(&sc->sc_dev, "isabus", &iba, isabrprint);
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}
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int
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isabrprint(void *aux, const char *pnp)
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{
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if (pnp)
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aprint_normal("isa at %s", pnp);
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aprint_verbose(" isa_io_base 0x%lx isa_mem_base 0x%lx",
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arc_bus_io.bs_vbase, arc_bus_mem.bs_vbase);
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return (UNCONF);
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}
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/*
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* Interrupt system driver code
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* ============================
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*/
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#define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != 2)
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int imen;
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int intrtype[ICU_LEN], intrmask[ICU_LEN], intrlevel[ICU_LEN];
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struct intrhand *intrhand[ICU_LEN];
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int fakeintr(void *a)
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{
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return 0;
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}
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/*
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* Recalculate the interrupt masks from scratch.
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* We could code special registry and deregistry versions of this function that
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* would be faster, but the code would be nastier, and we don't expect this to
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* happen very much anyway.
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*/
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void
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intr_calculatemasks(void)
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{
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int irq, level;
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struct intrhand *q;
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/* First, figure out which levels each IRQ uses. */
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for (irq = 0; irq < ICU_LEN; irq++) {
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int levels = 0;
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for (q = intrhand[irq]; q; q = q->ih_next)
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levels |= 1 << q->ih_level;
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intrlevel[irq] = levels;
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}
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/* Then figure out which IRQs use each level. */
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for (level = 0; level < _IPL_N; level++) {
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int irqs = 0;
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for (irq = 0; irq < ICU_LEN; irq++)
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if (intrlevel[irq] & (1 << level))
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irqs |= 1 << irq;
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imask[level] = irqs;
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}
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imask[IPL_NONE] = 0;
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imask[IPL_SOFT] |= imask[IPL_NONE];
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imask[IPL_SOFTCLOCK] |= imask[IPL_SOFT];
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imask[IPL_SOFTNET] |= imask[IPL_SOFTCLOCK];
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imask[IPL_SOFTSERIAL] |= imask[IPL_SOFTNET];
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/*
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* Enforce a hierarchy that gives slow devices a better chance at not
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* dropping data.
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*/
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imask[IPL_BIO] |= imask[IPL_SOFTSERIAL];
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imask[IPL_NET] |= imask[IPL_BIO];
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imask[IPL_TTY] |= imask[IPL_NET];
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/*
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* Since run queues may be manipulated by both the statclock and tty,
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* network, and diskdrivers, clock > tty.
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*/
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imask[IPL_CLOCK] |= imask[IPL_TTY];
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imask[IPL_STATCLOCK] |= imask[IPL_CLOCK];
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/*
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* IPL_HIGH must block everything that can manipulate a run queue.
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*/
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imask[IPL_HIGH] |= imask[IPL_STATCLOCK];
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/* And eventually calculate the complete masks. */
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for (irq = 0; irq < ICU_LEN; irq++) {
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int irqs = 1 << irq;
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for (q = intrhand[irq]; q; q = q->ih_next)
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irqs |= imask[q->ih_level];
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intrmask[irq] = irqs;
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}
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/* Lastly, determine which IRQs are actually in use. */
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{
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int irqs = 0;
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for (irq = 0; irq < ICU_LEN; irq++)
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if (intrhand[irq])
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irqs |= 1 << irq;
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if (irqs >= 0x100) /* any IRQs >= 8 in use */
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irqs |= 1 << IRQ_SLAVE;
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imen = ~irqs;
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isa_outb(IO_ICU1 + 1, imen);
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isa_outb(IO_ICU2 + 1, imen >> 8);
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}
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}
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void
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isabr_attach_hook(struct device *parent, struct device *self,
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struct isabus_attach_args *iba)
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{
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/* Nothing to do. */
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}
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const struct evcnt *
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isabr_intr_evcnt(isa_chipset_tag_t ic, int irq)
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{
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/* XXX for now, no evcnt parent reported */
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return NULL;
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}
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/*
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* Establish a ISA bus interrupt.
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*/
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void *
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isabr_intr_establish(isa_chipset_tag_t ic, int irq, int type, int level,
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int (*ih_fun)(void *), void *ih_arg)
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{
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struct intrhand **p, *q, *ih;
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static struct intrhand fakehand = {NULL, fakeintr};
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/* no point in sleeping unless someone can free memory. */
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ih = malloc(sizeof *ih, M_DEVBUF, cold ? M_NOWAIT : M_WAITOK);
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if (ih == NULL)
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panic("isa_intr_establish: can't malloc handler info");
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if (!LEGAL_IRQ(irq) || type == IST_NONE)
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panic("intr_establish: bogus irq or type");
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switch (intrtype[irq]) {
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case IST_NONE:
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intrtype[irq] = type;
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break;
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case IST_EDGE:
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case IST_LEVEL:
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if (type == intrtype[irq])
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break;
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case IST_PULSE:
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if (type != IST_NONE)
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panic("intr_establish: can't share %s with %s",
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isa_intr_typename(intrtype[irq]),
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isa_intr_typename(type));
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break;
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}
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/*
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* Figure out where to put the handler.
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* This is O(N^2), but we want to preserve the order, and N is
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* generally small.
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*/
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for (p = &intrhand[irq]; (q = *p) != NULL; p = &q->ih_next)
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;
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/*
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* Actually install a fake handler momentarily, since we might be doing
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* this with interrupts enabled and don't want the real routine called
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* until masking is set up.
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*/
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fakehand.ih_level = level;
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*p = &fakehand;
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intr_calculatemasks();
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/*
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* Poke the real handler in now.
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*/
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ih->ih_fun = ih_fun;
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ih->ih_arg = ih_arg;
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ih->ih_count = 0;
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ih->ih_next = NULL;
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ih->ih_level = level;
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ih->ih_irq = irq;
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ih->ih_what = ""; /* XXX - should be eliminated */
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*p = ih;
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return ih;
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}
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void
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isabr_intr_disestablish(isa_chipset_tag_t ic, void *arg)
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{
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}
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/*
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* Process an interrupt from the ISA bus.
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*/
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uint32_t
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isabr_iointr(uint32_t mask, struct clockframe *cf)
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{
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struct intrhand *ih;
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int isa_vector;
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int o_imen;
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isa_vector = (*isabr_conf->ic_intr_status)();
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if (isa_vector < 0)
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return (~0);
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o_imen = imen;
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imen |= 1 << (isa_vector & (ICU_LEN - 1));
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if (isa_vector & 0x08) {
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isa_inb(IO_ICU2 + 1);
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isa_outb(IO_ICU2 + 1, imen >> 8);
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isa_outb(IO_ICU2, 0x60 + (isa_vector & 7));
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isa_outb(IO_ICU1, 0x60 + IRQ_SLAVE);
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} else {
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isa_inb(IO_ICU1 + 1);
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isa_outb(IO_ICU1 + 1, imen);
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isa_outb(IO_ICU1, 0x60 + isa_vector);
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}
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ih = intrhand[isa_vector];
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if (isa_vector == 0) { /* Clock */ /*XXX*/
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last_cp0_count = mips3_cp0_count_read();
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(*ih->ih_fun)(cf);
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ih = ih->ih_next;
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}
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while (ih) {
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(*ih->ih_fun)(ih->ih_arg);
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ih = ih->ih_next;
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}
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imen = o_imen;
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isa_inb(IO_ICU1 + 1);
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isa_inb(IO_ICU2 + 1);
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isa_outb(IO_ICU1 + 1, imen);
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isa_outb(IO_ICU2 + 1, imen >> 8);
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return ~MIPS_INT_MASK_2;
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}
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/*
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* Initialize the Interrupt controller logic.
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*/
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void
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isabr_initicu(void)
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{
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int i;
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for (i = 0; i < ICU_LEN; i++) {
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switch (i) {
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case 2:
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case 8:
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intrtype[i] = IST_EDGE;
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break;
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default:
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intrtype[i] = IST_NONE;
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break;
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}
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}
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isa_outb(IO_ICU1, 0x11); /* reset; program device, four bytes */
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isa_outb(IO_ICU1+1, 0); /* starting at this vector index */
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isa_outb(IO_ICU1+1, 1 << IRQ_SLAVE); /* slave on line 2 */
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isa_outb(IO_ICU1+1, 1); /* 8086 mode */
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isa_outb(IO_ICU1+1, 0xff); /* leave interrupts masked */
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isa_outb(IO_ICU1, 0x68); /* special mask mode (if available) */
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isa_outb(IO_ICU1, 0x0a); /* Read IRR by default. */
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#ifdef REORDER_IRQ
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isa_outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */
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#endif
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isa_outb(IO_ICU2, 0x11); /* reset; program device, four bytes */
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isa_outb(IO_ICU2+1, 8); /* staring at this vector index */
|
|
isa_outb(IO_ICU2+1, IRQ_SLAVE);
|
|
isa_outb(IO_ICU2+1, 1); /* 8086 mode */
|
|
isa_outb(IO_ICU2+1, 0xff); /* leave interrupts masked */
|
|
isa_outb(IO_ICU2, 0x68); /* special mask mode (if available) */
|
|
isa_outb(IO_ICU2, 0x0a); /* Read IRR by default. */
|
|
}
|
|
|
|
|
|
/*
|
|
* SPEAKER BEEPER...
|
|
*/
|
|
void
|
|
sysbeepstop(void *arg)
|
|
{
|
|
int s;
|
|
|
|
/* disable counter 2 */
|
|
s = splhigh();
|
|
isa_outb(PITAUX_PORT, isa_inb(PITAUX_PORT) & ~PIT_SPKR);
|
|
splx(s);
|
|
beeping = 0;
|
|
}
|
|
|
|
void
|
|
sysbeep(int pitch, int period)
|
|
{
|
|
static int last_pitch, last_period;
|
|
int s;
|
|
|
|
if (cold)
|
|
return; /* Can't beep yet. */
|
|
|
|
if (beeping)
|
|
callout_stop(&sysbeep_ch);
|
|
if (!beeping || last_pitch != pitch) {
|
|
s = splhigh();
|
|
isa_outb(IO_TIMER1 + TIMER_MODE,
|
|
TIMER_SEL2 | TIMER_16BIT | TIMER_SQWAVE);
|
|
isa_outb(IO_TIMER1 + TIMER_CNTR2, TIMER_DIV(pitch) % 256);
|
|
isa_outb(IO_TIMER1 + TIMER_CNTR2, TIMER_DIV(pitch) / 256);
|
|
isa_outb(PITAUX_PORT, isa_inb(PITAUX_PORT) | PIT_SPKR);
|
|
splx(s);
|
|
}
|
|
last_pitch = pitch;
|
|
beeping = last_period = period;
|
|
callout_reset(&sysbeep_ch, period, sysbeepstop, NULL);
|
|
}
|
|
|
|
int
|
|
isa_intr_alloc(isa_chipset_tag_t c, int mask, int type, int *irq_p)
|
|
{
|
|
int irq;
|
|
int maybe_irq = -1;
|
|
int shared_depth = 0;
|
|
mask &= 0x8b28; /* choose from 3, 5, 8, 9, 11, 15 XXX */
|
|
for (irq = 0; mask != 0; mask >>= 1, irq++) {
|
|
if ((mask & 1) == 0)
|
|
continue;
|
|
if (intrtype[irq] == IST_NONE) {
|
|
*irq_p = irq;
|
|
return 0;
|
|
}
|
|
/* Level interrupts can be shared */
|
|
if (type == IST_LEVEL && intrtype[irq] == IST_LEVEL) {
|
|
struct intrhand *ih = intrhand[irq];
|
|
int depth;
|
|
if (maybe_irq == -1) {
|
|
maybe_irq = irq;
|
|
continue;
|
|
}
|
|
for (depth = 0; ih != NULL; ih = ih->ih_next)
|
|
depth++;
|
|
if (depth < shared_depth) {
|
|
maybe_irq = irq;
|
|
shared_depth = depth;
|
|
}
|
|
}
|
|
}
|
|
if (maybe_irq != -1) {
|
|
*irq_p = maybe_irq;
|
|
return 0;
|
|
}
|
|
return 1;
|
|
}
|