1884f05354
Remove the entire idea of fasttrap interrupts since V9 traps are really cheap, the CPUs are really fast, and the completely different trap frames would make these handlers really difficult to implement. pmap_changeprot() was only used by the clock and one other place; deprecate it. probeget() and probeset() now take 64-bit addresses even in 32-bit mode so we can probe IO locations by physical addresses. Some pmap cleanup. Some more copyright cleanup.
183 lines
5.8 KiB
C
183 lines
5.8 KiB
C
/* $NetBSD: pmap.h,v 1.10 1999/06/07 05:28:04 eeh Exp $ */
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/*-
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* Copyright (C) 1995, 1996 Wolfgang Solfrank.
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* Copyright (C) 1995, 1996 TooLs GmbH.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by TooLs GmbH.
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* 4. The name of TooLs GmbH may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MACHINE_PMAP_H_
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#define _MACHINE_PMAP_H_
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#ifndef _LOCORE
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#include <machine/pte.h>
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#include <sys/queue.h>
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#endif
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/*
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* This scheme uses 2-level page tables.
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*
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* While we're still in 32-bit mode we do the following:
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*
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* offset: 13 bits
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* 1st level: 1024 64-bit TTEs in an 8K page for 10 bits
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* 2nd level: 512 32-bit pointers in the pmap for 9 bits
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* -------
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* total: 32 bits
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*
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* In 64-bit mode the Spitfire and Blackbird CPUs support only
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* 44-bit virtual addresses. All addresses between
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* 0x0000 07ff ffff ffff and 0xffff f800 0000 0000 are in the
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* "VA hole" and trap, so we don't have to track them. However,
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* we do need to keep them in mind during PT walking. If they
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* ever change the size of the address "hole" we need to rework
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* all the page table handling.
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*
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* offset: 13 bits
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* 1st level: 1024 64-bit TTEs in an 8K page for 10 bits
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* 2nd level: 1024 64-bit pointers in an 8K page for 10 bits
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* 3rd level: 1024 64-bit pointers in the segmap for 10 bits
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* -------
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* total: 43 bits
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*
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* Of course, this means for 32-bit spaces we always have a (practically)
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* wasted page for the segmap (only one entry used) and half a page wasted
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* for the page directory. We still have need of one extra bit 8^(.
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*/
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#define HOLESHIFT (43)
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#define PTSZ (NBPG/8)
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#define PDSZ (PTSZ)
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#define STSZ (PTSZ)
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#define PTSHIFT (13)
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#define PDSHIFT (10+PTSHIFT)
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#define STSHIFT (10+PDSHIFT)
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#define PTMASK (PTSZ-1)
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#define PDMASK (PDSZ-1)
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#define STMASK (STSZ-1)
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#ifndef _LOCORE
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/*
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* Support for big page sizes. This maps the page size to the
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* page bits.
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*/
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struct page_size_map {
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u_int64_t mask;
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u_int64_t code;
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#ifdef DEBUG
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u_int64_t use;
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#endif
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};
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extern struct page_size_map page_size_map[];
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/*
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* Pmap stuff
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*/
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#define va_to_seg(v) (int)((((paddr_t)(v))>>STSHIFT)&STMASK)
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#define va_to_dir(v) (int)((((paddr_t)(v))>>PDSHIFT)&PDMASK)
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#define va_to_pte(v) (int)((((paddr_t)(v))>>PTSHIFT)&PTMASK)
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struct pmap {
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int pm_ctx; /* Current context */
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int pm_refs; /* ref count */
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/*
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* This contains 64-bit pointers to pages that contain
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* 1024 64-bit pointers to page tables. All addresses
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* are physical.
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*
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* !!! Only touch this through pseg_get() and pseg_set() !!!
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*/
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paddr_t pm_physaddr; /* physical address of pm_segs */
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int64_t *pm_segs;
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};
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/*
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* This comes from the PROM and is used to map prom entries.
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*/
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struct prom_map {
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u_int64_t vstart;
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u_int64_t vsize;
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u_int64_t tte;
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};
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#define PMAP_NC 0x001 /* Set the E bit in the page */
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#define PMAP_NVC 0x002 /* Don't enable the virtual cache */
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#define PMAP_LITTLE 0x004 /* Map in little endian mode */
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/* Large page size hints -- we really should use another param to pmap_enter() */
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#define PMAP_8K 0x000
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#define PMAP_64K 0x008 /* Use 64K page */
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#define PMAP_512K 0x010
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#define PMAP_4M 0x018
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#define PMAP_SZ_TO_TTE(x) (((x)&0x018)<<58)
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/* If these bits are different in va's to the same PA then there is an aliasing in the d$ */
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#define VA_ALIAS_MASK (1<<14)
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typedef struct pmap *pmap_t;
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/*
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* Encode IO space for pmap_enter()
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*
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* Since sun4u machines don't have separate IO spaces, this is a noop.
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*/
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#define PMAP_IOENC(io) 0
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#ifdef _KERNEL
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extern struct pmap kernel_pmap_;
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#define pmap_kernel() (&kernel_pmap_)
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int pmap_count_res __P((pmap_t pmap));
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/* int pmap_change_wiring __P((pmap_t pm, vaddr_t va, boolean_t wired)); */
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#define pmap_resident_count(pm) pmap_count_res((pm))
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#define pmap_from_phys_address(x,f) ((x)>>PGSHIFT)
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#define pmap_phys_address(x) ((((paddr_t)(x))<<PGSHIFT)|PMAP_NC)
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void pmap_bootstrap __P((u_long kernelstart, u_long kernelend, u_int numctx));
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/* SPARC specific? */
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void pmap_redzone __P((void));
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int pmap_dumpsize __P((void));
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int pmap_dumpmmu __P((int (*)__P((dev_t, daddr_t, caddr_t, size_t)),
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daddr_t));
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int pmap_pa_exists __P((paddr_t));
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struct proc;
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void switchexit __P((struct proc *));
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/* SPARC64 specific */
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int ctx_alloc __P((struct pmap*));
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void ctx_free __P((struct pmap*));
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#endif /* _KERNEL */
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#endif /* _LOCORE */
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#endif /* _MACHINE_PMAP_H_ */
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