383 lines
7.5 KiB
C
383 lines
7.5 KiB
C
/* $NetBSD: ixp12x0_io.c,v 1.2 2002/09/27 15:35:48 provos Exp $ */
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/*
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* Copyright (c) 2002
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* Ichiro FUKUHARA <ichiro@ichiro.org>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Ichiro FUKUHARA.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* bus_space I/O functions for ixp12x0
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/queue.h>
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#include <uvm/uvm.h>
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#include <machine/bus.h>
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#include <arm/ixp12x0/ixp12x0reg.h>
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#include <arm/ixp12x0/ixp12x0var.h>
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/* Proto types for all the bus_space structure functions */
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bs_protos(ixp12x0);
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bs_protos(ixp12x0_io);
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bs_protos(ixp12x0_mem);
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bs_protos(generic);
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bs_protos(generic_armv4);
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bs_protos(bs_notimpl);
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struct bus_space ixp12x0_bs_tag = {
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/* cookie */
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(void *) 0,
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/* mapping/unmapping */
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NULL,
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NULL,
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ixp12x0_bs_subregion,
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/* allocation/deallocation */
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NULL,
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NULL,
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/* get kernel virtual address */
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ixp12x0_bs_vaddr,
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/* mmap bus space for userland */
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ixp12x0_bs_mmap,
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/* barrier */
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ixp12x0_bs_barrier,
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/* read (single) */
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generic_bs_r_1,
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generic_armv4_bs_r_2,
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generic_bs_r_4,
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bs_notimpl_bs_r_8,
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/* read multiple */
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generic_bs_rm_1,
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generic_armv4_bs_rm_2,
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generic_bs_rm_4,
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bs_notimpl_bs_rm_8,
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/* read region */
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bs_notimpl_bs_rr_1,
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generic_armv4_bs_rr_2,
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generic_bs_rr_4,
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bs_notimpl_bs_rr_8,
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/* write (single) */
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generic_bs_w_1,
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generic_armv4_bs_w_2,
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generic_bs_w_4,
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bs_notimpl_bs_w_8,
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/* write multiple */
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generic_bs_wm_1,
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generic_armv4_bs_wm_2,
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generic_bs_wm_4,
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bs_notimpl_bs_wm_8,
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/* write region */
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bs_notimpl_bs_wr_1,
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generic_armv4_bs_wr_2,
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bs_notimpl_bs_wr_4,
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bs_notimpl_bs_wr_8,
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/* set multiple */
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bs_notimpl_bs_sm_1,
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bs_notimpl_bs_sm_2,
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bs_notimpl_bs_sm_4,
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bs_notimpl_bs_sm_8,
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/* set region */
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bs_notimpl_bs_sr_1,
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generic_armv4_bs_sr_2,
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bs_notimpl_bs_sr_4,
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bs_notimpl_bs_sr_8,
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/* copy */
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bs_notimpl_bs_c_1,
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generic_armv4_bs_c_2,
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bs_notimpl_bs_c_4,
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bs_notimpl_bs_c_8,
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};
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void
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ixp12x0_bs_init(bs, cookie)
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bus_space_tag_t bs;
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void *cookie;
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{
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*bs = ixp12x0_bs_tag;
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bs->bs_cookie = cookie;
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}
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void
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ixp12x0_io_bs_init(bs, cookie)
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bus_space_tag_t bs;
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void *cookie;
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{
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*bs = ixp12x0_bs_tag;
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bs->bs_cookie = cookie;
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bs->bs_map = ixp12x0_io_bs_map;
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bs->bs_unmap = ixp12x0_io_bs_unmap;
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bs->bs_alloc = ixp12x0_io_bs_alloc;
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bs->bs_free = ixp12x0_io_bs_free;
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bs->bs_vaddr = ixp12x0_io_bs_vaddr;
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}
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void
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ixp12x0_mem_bs_init(bs, cookie)
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bus_space_tag_t bs;
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void *cookie;
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{
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*bs = ixp12x0_bs_tag;
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bs->bs_cookie = cookie;
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bs->bs_map = ixp12x0_mem_bs_map;
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bs->bs_unmap = ixp12x0_mem_bs_unmap;
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bs->bs_alloc = ixp12x0_mem_bs_alloc;
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bs->bs_free = ixp12x0_mem_bs_free;
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bs->bs_mmap = ixp12x0_mem_bs_mmap;
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}
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/* mem bus space functions */
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int
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ixp12x0_mem_bs_map(t, bpa, size, cacheable, bshp)
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void *t;
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bus_addr_t bpa;
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bus_size_t size;
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int cacheable;
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bus_space_handle_t *bshp;
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{
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#if 0
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struct ixp12x0_softc *sc = t;
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#endif
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paddr_t pa, endpa;
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vaddr_t va;
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if ((bpa + size) >= IXP12X0_PCI_MEM_SIZE)
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return (EINVAL);
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/*
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* PCI MEM space is mapped same address as real memory
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*/
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pa = trunc_page(bpa + IXP12X0_PCI_MEM_VBASE);
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endpa = round_page((bpa + IXP12X0_PCI_MEM_VBASE) + size);
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/* XXX use extent manager to check duplicate mapping */
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va = uvm_km_valloc(kernel_map, endpa - pa);
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if (va == 0)
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return(ENOMEM);
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/* Store the bus space handle */
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*bshp = va + (bpa & PAGE_MASK);
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for(; pa < endpa; pa += PAGE_SIZE, va += PAGE_SIZE) {
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pmap_enter(pmap_kernel(), va, pa,
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VM_PROT_READ | VM_PROT_WRITE, PMAP_WIRED);
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}
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pmap_update(pmap_kernel());
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return(0);
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}
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void
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ixp12x0_mem_bs_unmap(t, bsh, size)
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void *t;
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bus_space_handle_t bsh;
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bus_size_t size;
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{
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vaddr_t startva, endva;
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startva = trunc_page(bsh);
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endva = round_page(bsh + size);
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uvm_km_free(kernel_map, startva, endva - startva);
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}
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int
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ixp12x0_mem_bs_alloc(t, rstart, rend, size, alignment, boundary, cacheable,
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bpap, bshp)
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void *t;
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bus_addr_t rstart, rend;
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bus_size_t size, alignment, boundary;
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int cacheable;
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bus_addr_t *bpap;
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bus_space_handle_t *bshp;
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{
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panic("ixp12x0_mem_bs_alloc(): Help!");
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}
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void
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ixp12x0_mem_bs_free(t, bsh, size)
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void *t;
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bus_space_handle_t bsh;
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bus_size_t size;
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{
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panic("ixp12x0_mem_bs_free(): Help!");
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}
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paddr_t
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ixp12x0_mem_bs_mmap(t, addr, off, prot, flags)
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void *t;
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bus_addr_t addr;
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off_t off;
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int prot;
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int flags;
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{
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/* Not supported. */
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return (-1);
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}
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/* I/O bus space functions */
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int
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ixp12x0_io_bs_map(t, bpa, size, cacheable, bshp)
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void *t;
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bus_addr_t bpa;
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bus_size_t size;
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int cacheable;
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bus_space_handle_t *bshp;
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{
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#if 0
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struct ixp12x0_softc *sc = t;
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#endif
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#if 0
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if ((bpa + size) >= IXP12X0_PCI_IO_SIZE)
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return (EINVAL);
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#endif
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/*
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* PCI I/O space is mapped at virtual address of each evaluation board.
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* Translate the bus address to the virtual address.
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*/
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*bshp = bpa + IXP12X0_PCI_IO_VBASE;
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return(0);
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}
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void
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ixp12x0_io_bs_unmap(t, bsh, size)
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void *t;
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bus_space_handle_t bsh;
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bus_size_t size;
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{
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/*
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* Temporary implementation
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*/
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}
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int
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ixp12x0_io_bs_alloc(t, rstart, rend, size, alignment, boundary, cacheable,
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bpap, bshp)
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void *t;
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bus_addr_t rstart, rend;
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bus_size_t size, alignment, boundary;
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int cacheable;
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bus_addr_t *bpap;
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bus_space_handle_t *bshp;
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{
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panic("ixp12x0_io_bs_alloc(): Help!");
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}
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void
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ixp12x0_io_bs_free(t, bsh, size)
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void *t;
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bus_space_handle_t bsh;
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bus_size_t size;
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{
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panic("ixp12x0_io_bs_free(): Help!");
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}
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void *
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ixp12x0_io_bs_vaddr(t, bsh)
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void *t;
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bus_space_handle_t bsh;
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{
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/* Not supported. */
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return (NULL);
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}
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/* Common routines */
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int
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ixp12x0_bs_subregion(t, bsh, offset, size, nbshp)
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void *t;
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bus_space_handle_t bsh;
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bus_size_t offset, size;
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bus_space_handle_t *nbshp;
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{
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*nbshp = bsh + offset;
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return (0);
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}
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void *
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ixp12x0_bs_vaddr(t, bsh)
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void *t;
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bus_space_handle_t bsh;
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{
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return ((void *)bsh);
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}
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paddr_t
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ixp12x0_bs_mmap(t, addr, off, prot, flags)
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void *t;
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bus_addr_t addr;
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off_t off;
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int prot;
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int flags;
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{
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/* Not supported. */
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return (-1);
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}
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void
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ixp12x0_bs_barrier(t, bsh, offset, len, flags)
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void *t;
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bus_space_handle_t bsh;
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bus_size_t offset, len;
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int flags;
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{
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/* NULL */
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}
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/* End of ixp12x0_io.c */
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