668 lines
17 KiB
C
668 lines
17 KiB
C
/* $NetBSD: vrc4172gpio.c,v 1.11 2006/03/29 04:16:45 thorpej Exp $ */
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/*-
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* Copyright (c) 2001 TAKEMRUA Shin. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the project nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: vrc4172gpio.c,v 1.11 2006/03/29 04:16:45 thorpej Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <sys/queue.h>
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#include <sys/reboot.h>
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#include <machine/bus.h>
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#include <machine/platid.h>
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#include <machine/platid_mask.h>
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#include <dev/hpc/hpciovar.h>
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#include <hpcmips/vr/vripif.h>
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#include <hpcmips/vr/vripvar.h>
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#include <hpcmips/vr/vrc4172gpioreg.h>
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#include "locators.h"
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#define VRC2GPIODEBUG
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#ifdef VRC2GPIODEBUG
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#define DBG_IO (1<<0)
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#define DBG_INTR (1<<1)
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#define DBG_INFO (1<<2)
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#ifndef VRC2GPIODEBUG_CONF
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#define VRC2GPIODEBUG_CONF 0
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#endif /* VRC2GPIODEBUG_CONF */
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int vrc4172gpio_debug = VRC2GPIODEBUG_CONF;
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#define DBG(flag) (vrc4172gpio_debug & (flag))
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#define DPRINTF(flag, arg...) do { \
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if (DBG(flag)) \
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printf(arg); \
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} while (0)
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#else
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#define DBG(flag) (0)
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#define DPRINTF(flag, arg...) do {} while(0)
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#endif
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#define VPRINTF(arg...) do { \
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if (bootverbose) \
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printf(##arg); \
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} while (0)
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#define CHECK_PORT(x) (0 <= (x) && (x) < VRC2_EXGP_NPORTS)
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struct vrc4172gpio_intr_entry {
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int ih_port;
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int (*ih_fun)(void*);
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void *ih_arg;
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TAILQ_ENTRY(vrc4172gpio_intr_entry) ih_link;
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};
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struct vrc4172gpio_softc {
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struct device sc_dev;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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struct hpcio_attach_args sc_args;
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struct hpcio_chip *sc_hc;
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void *sc_intr_handle;
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u_int32_t sc_intr_mask;
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u_int32_t sc_data;
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u_int32_t sc_intr_mode[VRC2_EXGP_NPORTS];
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TAILQ_HEAD(, vrc4172gpio_intr_entry) sc_intr_head[VRC2_EXGP_NPORTS];
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struct hpcio_chip sc_iochip;
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struct hpcio_attach_args sc_haa;
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};
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int vrc4172gpio_match(struct device*, struct cfdata*, void*);
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void vrc4172gpio_attach(struct device*, struct device*, void*);
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void vrc4172gpio_callback(struct device *self);
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int vrc4172gpio_intr(void*);
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int vrc4172gpio_print(void*, const char*);
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int vrc4172gpio_port_read(hpcio_chip_t, int);
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void vrc4172gpio_port_write(hpcio_chip_t, int, int);
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void *vrc4172gpio_intr_establish(hpcio_chip_t, int, int, int (*)(void *), void*);
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void vrc4172gpio_intr_disestablish(hpcio_chip_t, void*);
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void vrc4172gpio_intr_clear(hpcio_chip_t, void*);
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void vrc4172gpio_register_iochip(hpcio_chip_t, hpcio_chip_t);
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void vrc4172gpio_update(hpcio_chip_t);
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void vrc4172gpio_dump(hpcio_chip_t);
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void vrc4172gpio_intr_dump(struct vrc4172gpio_softc *, int);
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hpcio_chip_t vrc4172gpio_getchip(void*, int);
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static void vrc4172gpio_diffport(struct vrc4172gpio_softc *sc);
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static u_int16_t read_2(struct vrc4172gpio_softc *, bus_addr_t);
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static void write_2(struct vrc4172gpio_softc *, bus_addr_t, u_int16_t);
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static u_int32_t read_4(struct vrc4172gpio_softc *, bus_addr_t);
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static void write_4(struct vrc4172gpio_softc *, bus_addr_t, u_int32_t);
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static void dumpbits(u_int32_t*, int, int, int, const char[2]);
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static struct hpcio_chip vrc4172gpio_iochip = {
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.hc_portread = vrc4172gpio_port_read,
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.hc_portwrite = vrc4172gpio_port_write,
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.hc_intr_establish = vrc4172gpio_intr_establish,
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.hc_intr_disestablish = vrc4172gpio_intr_disestablish,
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.hc_intr_clear = vrc4172gpio_intr_clear,
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.hc_register_iochip = vrc4172gpio_register_iochip,
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.hc_update = vrc4172gpio_update,
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.hc_dump = vrc4172gpio_dump,
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};
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static int intlv_regs[] = {
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VRC2_EXGPINTLV0L,
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VRC2_EXGPINTLV0H,
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VRC2_EXGPINTLV1L
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};
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CFATTACH_DECL(vrc4172gpio, sizeof(struct vrc4172gpio_softc),
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vrc4172gpio_match, vrc4172gpio_attach, NULL, NULL);
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/*
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* regster access method
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*/
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static inline u_int16_t
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read_2(struct vrc4172gpio_softc *sc, bus_addr_t off)
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{
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return bus_space_read_2(sc->sc_iot, sc->sc_ioh, off);
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}
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static inline void
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write_2(struct vrc4172gpio_softc *sc, bus_addr_t off, u_int16_t data)
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{
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bus_space_write_2(sc->sc_iot, sc->sc_ioh, off, data);
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}
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static u_int32_t
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read_4(struct vrc4172gpio_softc *sc, bus_addr_t off)
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{
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u_int16_t reg0, reg1;
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reg0 = read_2(sc, off);
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reg1 = read_2(sc, off + VRC2_EXGP_OFFSET);
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return (reg0|(reg1<<16));
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}
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static void
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write_4(struct vrc4172gpio_softc *sc, bus_addr_t off, u_int32_t data)
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{
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write_2(sc, off, data & 0xffff);
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write_2(sc, off + VRC2_EXGP_OFFSET, (data>>16)&0xffff);
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}
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int
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vrc4172gpio_match(struct device *parent, struct cfdata *cf, void *aux)
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{
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struct hpcio_attach_args *haa = aux;
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platid_mask_t mask;
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if (strcmp(haa->haa_busname, HPCIO_BUSNAME))
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return (0);
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if (cf->cf_loc[HPCIOIFCF_PLATFORM] == 0)
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return (0);
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mask = PLATID_DEREF(cf->cf_loc[HPCIOIFCF_PLATFORM]);
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return platid_match(&platid, &mask);
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}
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void
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vrc4172gpio_attach(struct device *parent, struct device *self, void *aux)
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{
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struct hpcio_attach_args *args = aux;
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struct vrc4172gpio_softc *sc = (void*)self;
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int i, *loc, port, mode;
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u_int32_t regs[6], t0, t1, t2;
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printf("\n");
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loc = device_cfdata(&sc->sc_dev)->cf_loc;
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/*
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* map bus space
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*/
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sc->sc_iot = args->haa_iot;
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sc->sc_hc = (*args->haa_getchip)(args->haa_sc, loc[HPCIOIFCF_IOCHIP]);
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sc->sc_args = *args; /* structure copy */
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bus_space_map(sc->sc_iot, loc[HPCIOIFCF_ADDR], loc[HPCIOIFCF_SIZE],
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0 /* no cache */, &sc->sc_ioh);
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if (sc->sc_ioh == 0) {
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printf("%s: can't map bus space\n", sc->sc_dev.dv_xname);
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return;
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}
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/*
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* dump Windows CE register setting
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*/
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regs[0] = read_4(sc, VRC2_EXGPDATA);
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regs[1] = read_4(sc, VRC2_EXGPDIR);
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regs[2] = read_4(sc, VRC2_EXGPINTEN);
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regs[3] = read_4(sc, VRC2_EXGPINTTYP);
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t0 = read_2(sc, VRC2_EXGPINTLV0L);
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t1 = read_2(sc, VRC2_EXGPINTLV0H);
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t2 = read_2(sc, VRC2_EXGPINTLV1L);
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regs[4] = ((t2&0xff00)<<8) | (t1&0xff00) | ((t0&0xff00)>>8);
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regs[5] = ((t2&0xff)<<16) | ((t1&0xff)<<8) | (t0&0xff);
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if (bootverbose || DBG(DBG_INFO)) {
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/*
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* o: output
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* i: input (no interrupt)
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* H: level sense interrupt (active high)
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* L: level sense interrupt (active low)
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* B: both edge trigger interrupt
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* P: positive edge trigger interrupt
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* N: negative edge trigger interrupt
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*/
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printf(" port#:321098765432109876543210\n");
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printf(" EXGPDATA :");
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dumpbits(®s[0], 1, 23, 0, "10\n");
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printf("WIN setting:");
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dumpbits(®s[1], 5, 23, 0,
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"oooo" /* dir=1 en=1 typ=1 */
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"oooo" /* dir=1 en=1 typ=0 */
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"oooo" /* dir=1 en=0 typ=1 */
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"oooo" /* dir=1 en=0 typ=0 */
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"BBPN" /* dir=0 en=1 typ=1 */
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"HLHL" /* dir=0 en=1 typ=0 */
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"iiii" /* dir=0 en=0 typ=1 */
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"iiii" /* dir=0 en=0 typ=0 */
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);
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printf("\n");
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}
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#ifdef VRC2GPIODEBUG
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if (DBG(DBG_INFO)) {
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printf(" EXGPDIR :");
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dumpbits(®s[1], 1, 23, 0, "oi\n");
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printf(" EXGPINTEN :");
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dumpbits(®s[2], 1, 23, 0, "I-\n");
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printf(" EXGPINTTYP:");
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dumpbits(®s[3], 1, 23, 0, "EL\n");
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printf(" EXPIB :");
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dumpbits(®s[4], 1, 23, 0, "10\n");
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printf(" EXPIL :");
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dumpbits(®s[5], 1, 23, 0, "10\n");
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printf(" EXGPINTLV :%04x %04x %04x\n", t2, t1, t0);
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}
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#endif /* VRC2GPIODEBUG */
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/*
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* initialize register and internal data
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*/
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sc->sc_intr_mask = 0;
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write_2(sc, VRC2_EXGPINTEN, sc->sc_intr_mask);
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for (i = 0; i < VRC2_EXGP_NPORTS; i++)
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TAILQ_INIT(&sc->sc_intr_head[i]);
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sc->sc_data = read_4(sc, VRC2_EXGPDATA);
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if (bootverbose || DBG(DBG_INFO)) {
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u_int32_t data;
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sc->sc_intr_mask = (~read_4(sc, VRC2_EXGPDIR) & 0xffffff);
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write_4(sc, VRC2_EXGPINTTYP, 0); /* level sence interrupt */
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data = ~read_4(sc, VRC2_EXGPDATA);
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write_2(sc, VRC2_EXGPINTLV0L, (data >> 0) & 0xff);
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write_2(sc, VRC2_EXGPINTLV0H, (data >> 8) & 0xff);
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write_2(sc, VRC2_EXGPINTLV1L, (data >> 16) & 0xff);
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}
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/*
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* install interrupt handler
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*/
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port = loc[HPCIOIFCF_PORT];
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mode = HPCIO_INTR_LEVEL | HPCIO_INTR_HIGH;
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sc->sc_intr_handle =
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hpcio_intr_establish(sc->sc_hc, port, mode, vrc4172gpio_intr, sc);
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if (sc->sc_intr_handle == NULL) {
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printf("%s: can't establish interrupt\n", sc->sc_dev.dv_xname);
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return;
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}
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/*
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* fill hpcio_chip structure
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*/
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sc->sc_iochip = vrc4172gpio_iochip; /* structure copy */
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sc->sc_iochip.hc_chipid = VRIP_IOCHIP_VRC4172GPIO;
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sc->sc_iochip.hc_name = sc->sc_dev.dv_xname;
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sc->sc_iochip.hc_sc = sc;
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/* Register functions to upper interface */
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hpcio_register_iochip(sc->sc_hc, &sc->sc_iochip);
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/*
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* hpcio I/F
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*/
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sc->sc_haa.haa_busname = HPCIO_BUSNAME;
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sc->sc_haa.haa_sc = sc;
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sc->sc_haa.haa_getchip = vrc4172gpio_getchip;
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sc->sc_haa.haa_iot = sc->sc_iot;
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while (config_found(self, &sc->sc_haa, vrc4172gpio_print)) ;
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/*
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* GIU-ISA bridge
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*/
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#if 1 /* XXX Sometimes mounting root device failed. Why? XXX*/
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config_defer(self, vrc4172gpio_callback);
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#else
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vrc4172gpio_callback(self);
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#endif
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}
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void
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vrc4172gpio_callback(struct device *self)
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{
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struct vrc4172gpio_softc *sc = (void*)self;
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sc->sc_haa.haa_busname = "vrisab";
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config_found(self, &sc->sc_haa, vrc4172gpio_print);
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}
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int
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vrc4172gpio_print(void *aux, const char *pnp)
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{
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if (pnp)
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return (QUIET);
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return (UNCONF);
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}
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/*
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* PORT
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*/
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int
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vrc4172gpio_port_read(hpcio_chip_t hc, int port)
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{
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struct vrc4172gpio_softc *sc = hc->hc_sc;
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int on;
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if (!CHECK_PORT(port))
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panic("%s: illegal gpio port", __FUNCTION__);
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on = (read_4(sc, VRC2_EXGPDATA) & (1 << port));
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return (on ? 1 : 0);
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}
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void
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vrc4172gpio_port_write(hpcio_chip_t hc, int port, int onoff)
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{
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struct vrc4172gpio_softc *sc = hc->hc_sc;
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u_int32_t data;
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if (!CHECK_PORT(port))
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panic("%s: illegal gpio port", __FUNCTION__);
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data = read_4(sc, VRC2_EXGPDATA);
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if (onoff)
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data |= (1<<port);
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else
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data &= ~(1<<port);
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write_4(sc, VRC2_EXGPDATA, data);
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}
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void
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vrc4172gpio_update(hpcio_chip_t hc)
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{
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}
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void
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vrc4172gpio_intr_dump(struct vrc4172gpio_softc *sc, int port)
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{
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u_int32_t mask, mask2;
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int intlv_reg;
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mask = (1 << port);
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mask2 = (1 << (port % 8));
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intlv_reg = intlv_regs[port/8];
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if (read_4(sc, VRC2_EXGPDIR) & mask) {
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printf(" output");
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return;
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}
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printf(" input");
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if (read_4(sc, VRC2_EXGPINTTYP) & mask) {
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if (read_4(sc, intlv_reg) & (mask2 << 8)) {
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printf(", both edge");
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} else {
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if (read_4(sc, intlv_reg) & mask2)
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printf(", positive edge");
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else
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printf(", negative edge");
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}
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} else {
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if (read_4(sc, intlv_reg) & mask2)
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printf(", high level");
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else
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printf(", low level");
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}
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}
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static void
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vrc4172gpio_diffport(struct vrc4172gpio_softc *sc)
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{
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u_int32_t data;
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data = read_4(sc, VRC2_EXGPDATA);
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if (sc->sc_data != data) {
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printf(" port# 321098765432109876543210\n");
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printf("vrc4172data:");
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dumpbits(&data, 1, 23, 0, "10\n");
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/* bits which changed */
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data = (data & ~sc->sc_data)|(~data & sc->sc_data);
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printf(" ");
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dumpbits(&data, 1, 23, 0, "^ \n");
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sc->sc_data = data;
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}
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}
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static void
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dumpbits(u_int32_t *data, int ndata, int start, int end, const char *sym)
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{
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int i, j;
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if (start <= end)
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panic("%s(%d): %s", __FILE__, __LINE__, __FUNCTION__);
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for (i = start; end <= i; i--) {
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int d = 0;
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for (j = 0; j < ndata; j++)
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d = (d << 1) | ((data[j] & (1 << i)) ? 1 : 0);
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printf("%c", sym[(1 << ndata) - d - 1]);
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}
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if (sym[1<<ndata])
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printf("%c", sym[1<<ndata]);
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}
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void
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vrc4172gpio_dump(hpcio_chip_t hc)
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{
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}
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hpcio_chip_t
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vrc4172gpio_getchip(void* scx, int chipid)
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{
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struct vrc4172gpio_softc *sc = scx;
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return (&sc->sc_iochip);
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}
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/*
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* Interrupt staff
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*/
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void *
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vrc4172gpio_intr_establish(
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hpcio_chip_t hc,
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int port, /* GPIO pin # */
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int mode, /* GIU trigger setting */
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int (*ih_fun)(void*),
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void *ih_arg)
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{
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struct vrc4172gpio_softc *sc = hc->hc_sc;
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int s;
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u_int32_t reg, mask, mask2;
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struct vrc4172gpio_intr_entry *ih;
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int intlv_reg;
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s = splhigh();
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if (!CHECK_PORT(port))
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panic ("%s: bogus interrupt line", __FUNCTION__);
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if (sc->sc_intr_mode[port] && mode != sc->sc_intr_mode[port])
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panic ("%s: bogus interrupt type", __FUNCTION__);
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else
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sc->sc_intr_mode[port] = mode;
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mask = (1 << port);
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mask2 = (1 << (port % 8));
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intlv_reg = intlv_regs[port/8];
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ih = malloc(sizeof(struct vrc4172gpio_intr_entry), M_DEVBUF, M_NOWAIT);
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if (ih == NULL)
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panic("%s: no memory", __FUNCTION__);
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ih->ih_port = port;
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ih->ih_fun = ih_fun;
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ih->ih_arg = ih_arg;
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TAILQ_INSERT_TAIL(&sc->sc_intr_head[port], ih, ih_link);
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#ifdef VRC2GPIODEBUG
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if (DBG(DBG_INFO)) {
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printf("port %2d:", port);
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vrc4172gpio_intr_dump(sc, port);
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printf("->");
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}
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#endif
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/*
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* Setup registers
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*/
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/* I/O direction */
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reg = read_4(sc, VRC2_EXGPDIR);
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reg &= ~mask;
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write_4(sc, VRC2_EXGPDIR, reg);
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/* interrupt triger (level/edge) */
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reg = read_4(sc, VRC2_EXGPINTTYP);
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if (mode & HPCIO_INTR_EDGE)
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reg |= mask; /* edge */
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else
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reg &= ~mask; /* level */
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write_4(sc, VRC2_EXGPINTTYP, reg);
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/* interrupt trigger option */
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reg = read_4(sc, intlv_reg);
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if (mode & HPCIO_INTR_EDGE) {
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switch (mode & (HPCIO_INTR_POSEDGE | HPCIO_INTR_NEGEDGE)) {
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case HPCIO_INTR_POSEDGE:
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reg &= ~(mask2 << 8);
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reg |= mask2;
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break;
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case HPCIO_INTR_NEGEDGE:
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reg &= ~(mask2 << 8);
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reg &= ~mask2;
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break;
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case HPCIO_INTR_POSEDGE | HPCIO_INTR_NEGEDGE:
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default:
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reg |= (mask2 << 8);
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break;
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}
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} else {
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if (mode & HPCIO_INTR_HIGH)
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reg |= mask2; /* high */
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else
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reg &= ~mask2; /* low */
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}
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write_4(sc, intlv_reg, reg);
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#ifdef VRC2GPIODEBUG
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if (DBG(DBG_INFO)) {
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vrc4172gpio_intr_dump(sc, port);
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printf("\n");
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}
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#endif
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/* XXX, Vrc4172 doesn't have register to set hold or through */
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/*
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* clear interrupt status and enable interrupt
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*/
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vrc4172gpio_intr_clear(&sc->sc_iochip, ih);
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sc->sc_intr_mask |= mask;
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write_4(sc, VRC2_EXGPINTEN, sc->sc_intr_mask);
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splx(s);
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DPRINTF(DBG_INFO, "\n");
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return (ih);
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}
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void
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vrc4172gpio_intr_disestablish(hpcio_chip_t hc, void *arg)
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{
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struct vrc4172gpio_intr_entry *ihe = arg;
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struct vrc4172gpio_softc *sc = hc->hc_sc;
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int port = ihe->ih_port;
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struct vrc4172gpio_intr_entry *ih;
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int s;
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s = splhigh();
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TAILQ_FOREACH(ih, &sc->sc_intr_head[port], ih_link) {
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if (ih == ihe) {
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TAILQ_REMOVE(&sc->sc_intr_head[port], ih, ih_link);
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free(ih, M_DEVBUF);
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if (TAILQ_EMPTY(&sc->sc_intr_head[port])) {
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/* disable interrupt */
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sc->sc_intr_mask &= ~(1<<port);
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write_4(sc, VRC2_EXGPINTEN,
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sc->sc_intr_mask);
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}
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splx(s);
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return;
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}
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}
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panic("%s: no such a handle.", __FUNCTION__);
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/* NOTREACHED */
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}
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/* Clear interrupt */
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void
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vrc4172gpio_intr_clear(hpcio_chip_t hc, void *arg)
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{
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struct vrc4172gpio_softc *sc = hc->hc_sc;
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struct vrc4172gpio_intr_entry *ihe = arg;
|
|
|
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write_4(sc, VRC2_EXGPINTST, 1 << ihe->ih_port);
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write_4(sc, VRC2_EXGPINTST, 0);
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}
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|
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void
|
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vrc4172gpio_register_iochip(hpcio_chip_t hc, hpcio_chip_t iochip)
|
|
{
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struct vrc4172gpio_softc *sc = hc->hc_sc;
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hpcio_register_iochip(sc->sc_hc, iochip);
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}
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|
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/* interrupt handler */
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int
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vrc4172gpio_intr(void *arg)
|
|
{
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struct vrc4172gpio_softc *sc = arg;
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int i;
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u_int32_t reg;
|
|
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/* dispatch handler */
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reg = read_4(sc, VRC2_EXGPINTST);
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DPRINTF(DBG_INTR, "%s: EXGPINTST=%06x\n", __FUNCTION__, reg);
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for (i = 0; i < VRC2_EXGP_NPORTS; i++) {
|
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if (reg & (1 << i)) {
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|
register struct vrc4172gpio_intr_entry *ih;
|
|
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/*
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|
* call interrupt handler
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*/
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TAILQ_FOREACH(ih, &sc->sc_intr_head[i], ih_link) {
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ih->ih_fun(ih->ih_arg);
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}
|
|
|
|
/*
|
|
* disable interrupt if no handler is installed
|
|
*/
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if (TAILQ_EMPTY(&sc->sc_intr_head[i])) {
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sc->sc_intr_mask &= ~(1 << i);
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write_2(sc, VRC2_EXGPINTEN, sc->sc_intr_mask);
|
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/* dump EXGPDATA bits which changed */
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|
if (bootverbose || DBG(DBG_INFO))
|
|
vrc4172gpio_diffport(sc);
|
|
}
|
|
}
|
|
}
|
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|
return (0);
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|
}
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