7959c31a5f
epgpio: GPIO Interface (support gpio(4)) epled: LED on epgpio eppcic: PCMCIA Interface eprtc: Realtime clock epwdog: Watchdog timer changes ep93xx_intr: add dummy entries to keep vmstat happy. epclk: I use Timer1 and generate 100Hz if set. epe: attach epclk and epgpio first. fetch the Ethernet address from property if set. I use config flags and modify MDCDIV.
49 lines
2.3 KiB
C
49 lines
2.3 KiB
C
/* $NetBSD: eprtcreg.h,v 1.1 2005/11/12 05:33:23 hamajima Exp $ */
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/*
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* Copyright (c) 2005 HAMAJIMA Katsuomi. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* Cirrus Logic EP9315
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RealTime Clock register
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http://www.cirrus.com/jp/pubs/manual/EP9315_Users_Guide.pdf */
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#ifndef _EPRTCREG_H_
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#define _EPRTCREG_H_
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#define EP93XX_RTC_Data 0x00 /* RTC Data Register (RO) */
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#define EP93XX_RTC_Match 0x04 /* RTC Match Register (R/W) */
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#define EP93XX_RTC_Sts 0x08 /* RTC Status/EOI Register (R/W) */
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#define EP93XX_RTC_INTR (1<<0) /* Interrupt status */
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#define EP93XX_RTC_Load 0x0c /* RTC Load Register (R/W) */
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#define EP93XX_RTC_Ctrl 0x10 /* RTC Control Register (R/W) */
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#define EP93XX_RTC_MIE (1<<0) /* Match Interrupt Enable */
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#define EP93XX_RTC_SWComp 0x108 /* RTC Software Compensatin (R/W) */
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#define EP93XX_RTC_DEL_SHIFT (1<<16) /* Number of clocks to delete */
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#define EP93XX_RTC_DEL_MASK 0x001f0000
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#define EP93XX_RTC_INT_SHIFT (1<<0) /* Counter pre-load Interger value */
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#define EP93XX_RTC_INT_MASK 0x0000ffff
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#endif /* _EPRTCREG_H_ */
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