mjacob d5f967e27f Now that the underlying code for bus_dmamap_sync appears to do the ...

right thing, don't use the illegal and "just worked by chance" addition
of BUS_DMA_COHERENT to bus_dmamap_load_raw. There still is a necessity
to add to the architecture to allow one to hint that this should be
a cache coherent mapping.

Fix offset argument to be zero for flushing data tranfers. Kudos to Izumi
for spotting this.

2001-02-24 23:30:01 +00:00

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be.c

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bereg.h

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bpp.c

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bppreg.h

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bwtwo_sbus.c

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cgsix_sbus.c

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cgthree_sbus.c

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cs4231_sbus.c

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dma_sbus.c

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esp_sbus.c

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files.sbus

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if_en.c

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if_hme_sbus.c

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if_le_lebuffer.c

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if_le_ledma.c

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if_le.c

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isp_sbus.c

Now that the underlying code for bus_dmamap_sync appears to do the

2001-02-24 23:30:01 +00:00

lebuffer.c

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lebuffervar.h

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magma.c

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magmareg.h

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Makefile

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mbppio.h

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p9100.c

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qe.c

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qec.c

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qecreg.h

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qecvar.h

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qereg.h

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sbusvar.h

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stp4020.c

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stp4020reg.h

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tcx.c

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tcxreg.h

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xbox.c

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xboxvar.h

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