matt ee6cde04ff Don't use an asm in pmap_activate to update the TTBR, use cpu_setttb instead ... but add a second argument to it to indicate whether the TLB/caches need to be flushed. Default cortex to pmap_needs_fixup = 1. But check the MMFR3 field to see if the fixed can be skipped. Use a cf_flag bit 0 to indicate whether the A9 L2 cache should disable (bit 0 = 1) or enabeld (bit = 0). With these changes, the A9 MMU can use traverse caches to do MMU tablewalks Also, make sure all memory has the shareable bit for the A9.		2012-09-22 00:33:36 +00:00
..
g42xxeb_kmkbd.c	support WSDISPLAY_COMPAT_RAWKBD for TWINTAIL's on-board matrix keys.	2012-04-04 01:40:57 +00:00
g42xxeb_lcd.c
g42xxeb_machdep.c	Don't use an asm in pmap_activate to update the TTBR, use cpu_setttb instead	2012-09-22 00:33:36 +00:00
g42xxeb_mci.c	fix my license notice.	2012-01-21 19:44:28 +00:00
g42xxeb_reg.h
g42xxeb_start.S
g42xxeb_var.h
gb225_pcic.c	Don't set the iobase and iosize members of pcmciabus_attach_args because	2011-07-26 22:52:47 +00:00
gb225_slhci.c
gb225.c
gb225reg.h
gb225var.h
if_ne_obio.c
obio.c