150 lines
4.7 KiB
C
150 lines
4.7 KiB
C
/* $NetBSD: tegra_xusbpad.c,v 1.2 2015/12/13 17:39:19 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: tegra_xusbpad.c,v 1.2 2015/12/13 17:39:19 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/device.h>
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#include <sys/intr.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <arm/nvidia/tegra_reg.h>
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#include <arm/nvidia/tegra_xusbpadreg.h>
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#include <arm/nvidia/tegra_var.h>
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#include <dev/fdt/fdtvar.h>
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static int tegra_xusbpad_match(device_t, cfdata_t, void *);
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static void tegra_xusbpad_attach(device_t, device_t, void *);
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struct tegra_xusbpad_softc {
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device_t sc_dev;
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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};
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static struct tegra_xusbpad_softc *xusbpad_softc = NULL;
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CFATTACH_DECL_NEW(tegra_xusbpad, sizeof(struct tegra_xusbpad_softc),
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tegra_xusbpad_match, tegra_xusbpad_attach, NULL, NULL);
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static int
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tegra_xusbpad_match(device_t parent, cfdata_t cf, void *aux)
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{
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const char * const compatible[] =
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{ "nvidia,tegra124-xusb-padctl", NULL };
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struct fdt_attach_args * const faa = aux;
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return of_match_compatible(faa->faa_phandle, compatible);
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}
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static void
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tegra_xusbpad_attach(device_t parent, device_t self, void *aux)
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{
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struct tegra_xusbpad_softc * const sc = device_private(self);
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struct fdt_attach_args * const faa = aux;
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bus_addr_t addr;
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bus_size_t size;
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int error;
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if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) {
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aprint_error(": couldn't get registers\n");
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return;
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}
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sc->sc_dev = self;
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sc->sc_bst = faa->faa_bst;
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error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
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if (error) {
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aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error);
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return;
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}
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KASSERT(xusbpad_softc == NULL);
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xusbpad_softc = sc;
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aprint_naive("\n");
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aprint_normal(": XUSB PADCTL\n");
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}
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static void
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tegra_xusbpad_get_bs(bus_space_tag_t *pbst, bus_space_handle_t *pbsh)
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{
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if (xusbpad_softc) {
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*pbst = xusbpad_softc->sc_bst;
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*pbsh = xusbpad_softc->sc_bsh;
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} else {
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*pbst = &armv7_generic_bs_tag;
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bus_space_subregion(*pbst, tegra_apb_bsh,
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TEGRA_XUSB_PADCTL_OFFSET, TEGRA_XUSB_PADCTL_SIZE, pbsh);
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}
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}
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void
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tegra_xusbpad_sata_enable(void)
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{
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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int retry;
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tegra_xusbpad_get_bs(&bst, &bsh);
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tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_USB3_PAD_MUX_REG,
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__SHIFTIN(XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0_SATA,
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XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0) |
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XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0,
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XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0);
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tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_REG,
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0,
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XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ |
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XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD);
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tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG,
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0,
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XUSB_PADCTL_IOPHY_PLL_S0_CTL1_IDDQ |
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XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PWR_OVRD);
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tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG,
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XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE, 0);
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tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG,
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XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST, 0);
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for (retry = 1000; retry > 0; retry--) {
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const uint32_t v = bus_space_read_4(bst, bsh,
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XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG);
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if (v & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET)
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break;
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delay(100);
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}
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if (retry == 0) {
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printf("WARNING: SATA PHY power-on failed\n");
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}
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}
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