128 lines
5.4 KiB
C
128 lines
5.4 KiB
C
/* $NetBSD: tegra_usbreg.h,v 1.1 2015/10/21 20:02:12 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _ARM_TEGRA_USBREG_H
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#define _ARM_TEGRA_USBREG_H
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#define TEGRA_EHCI_TXFILLTUNING_REG 0x154
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#define TEGRA_EHCI_TXFILLTUNING_TXFIFOTHRES __BITS(21,16)
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#define TEGRA_EHCI_ICUSB_CTRL_REG 0x15c
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#define TEGRA_EHCI_ICUSB_CTRL_ENB1 __BIT(3)
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#define TEGRA_EHCI_ICUSB_CTRL_VDD1 __BITS(2,0)
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#define TEGRA_EHCI_HOSTPC1_DEVLC_REG 0x1b4
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#define TEGRA_EHCI_HOSTPC1_DEVLC_PTS __BITS(31,29)
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#define TEGRA_EHCI_HOSTPC1_DEVLC_PTS_UTMI 0
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#define TEGRA_EHCI_HOSTPC1_DEVLC_PTS_ULPI 2
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#define TEGRA_EHCI_HOSTPC1_DEVLC_PTS_ICUSB_SER 3
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#define TEGRA_EHCI_HOSTPC1_DEVLC_STS __BIT(28)
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#define TEGRA_EHCI_HOSTPC1_DEVLC_PTW __BIT(27)
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#define TEGRA_EHCI_HOSTPC1_DEVLC_PSPD __BITS(26,25)
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#define TEGRA_EHCI_HOSTPC1_DEVLC_PSPD_FS 0
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#define TEGRA_EHCI_HOSTPC1_DEVLC_PSPD_LS 1
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#define TEGRA_EHCI_HOSTPC1_DEVLC_PSPD_HS 2
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#define TEGRA_EHCI_HOSTPC1_DEVLC_ALPD __BIT(24)
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#define TEGRA_EHCI_HOSTPC1_DEVLC_PFSC __BIT(23)
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#define TEGRA_EHCI_HOSTPC1_DEVLC_PHCD __BIT(22)
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#define TEGRA_EHCI_HOSTPC1_DEVLC_H_LPMX __BITS(21,20)
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#define TEGRA_EHCI_HOSTPC1_DEVLC_H_EPLPM __BITS(19,16)
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#define TEGRA_EHCI_HOSTPC1_DEVLC_H_LPMFRM __BITS(15,12)
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#define TEGRA_EHCI_HOSTPC1_DEVLC_D_ASUS __BIT(17)
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#define TEGRA_EHCI_HOSTPC1_DEVLC_D_STL __BIT(16)
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#define TEGRA_EHCI_HOSTPC1_DEVLC_BA __BITS(11,1)
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#define TEGRA_EHCI_USBMODE_REG 0x1f8
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#define TEGRA_EHCI_USBMODE_CM __BITS(1,0)
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#define TEGRA_EHCI_USBMODE_CM_IDLE 0
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#define TEGRA_EHCI_USBMODE_CM_DEVICE 2
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#define TEGRA_EHCI_USBMODE_CM_HOST 3
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#define TEGRA_EHCI_SUSP_CTRL_REG 0x400
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#define TEGRA_EHCI_SUSP_CTRL_UHSIC_RESET __BIT(14)
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#define TEGRA_EHCI_SUSP_CTRL_ULPI_PHY_ENB __BIT(13)
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#define TEGRA_EHCI_SUSP_CTRL_UTMIP_PHY_ENB __BIT(12)
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#define TEGRA_EHCI_SUSP_CTRL_UTMIP_RESET __BIT(11)
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#define TEGRA_EHCI_SUSP_CTRL_PHY_CLK_VALID __BIT(7)
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#define TEGRA_EHCI_PHY_VBUS_SENSORS_REG 0x404
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#define TEGRA_EHCI_PHY_VBUS_SENSORS_A_VBUS_VLD_STS __BIT(26)
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#define TEGRA_EHCI_PHY_VBUS_SENSORS_B_VLD_SW_VALUE __BIT(12)
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#define TEGRA_EHCI_PHY_VBUS_SENSORS_B_VLD_SW_EN __BIT(11)
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#define TEGRA_EHCI_UTMIP_XCVR_CFG0_REG 0x808
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#define TEGRA_EHCI_UTMIP_XCVR_CFG0_HSSLEW_MSB __BITS(31,25)
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#define TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP_MSB __BITS(24,22)
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#define TEGRA_EHCI_UTMIP_XCVR_CFG0_LSBIAS_SEL __BIT(21)
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#define TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP __BITS(3,0)
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#define TEGRA_EHCI_UTMIP_XCVR_CFG0_PDZI_POWERDOWN __BIT(18)
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#define TEGRA_EHCI_UTMIP_XCVR_CFG0_PD2_POWERDOWN __BIT(16)
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#define TEGRA_EHCI_UTMIP_XCVR_CFG0_PD_POWERDOWN __BIT(14)
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#define TEGRA_EHCI_UTMIP_BIAS_CFG0_REG 0x80c
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#define TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL_MSB __BIT(24)
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#define TEGRA_EHCI_UTMIP_BIAS_CFG0_BIASPD __BIT(10)
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#define TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL __BITS(3,2)
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#define TEGRA_EHCI_UTMIP_TX_CFG0_REG 0x820
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#define TEGRA_EHCI_UTMIP_TX_CFG0_FS_PREAMBLE_J __BIT(19)
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#define TEGRA_EHCI_UTMIP_MISC_CFG0_REG 0x824
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#define TEGRA_EHCI_UTMIP_MISC_CFG0_SUSPEND_EXIT_ON_EDGE __BIT(22)
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#define TEGRA_EHCI_UTMIP_MISC_CFG1_REG 0x828
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#define TEGRA_EHCI_UTMIP_MISC_CFG1_PHY_XTAL_CLOCKEN __BIT(30)
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#define TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_REG 0x82c
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#define TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_B __BITS(31,16)
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#define TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_A __BITS(15,0)
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#define TEGRA_EHCI_UTMIP_BAT_CHRG_CFG0_REG 0x830
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#define TEGRA_EHCI_UTMIP_BAT_CHRG_CFG0_PD_CHRG __BIT(0)
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#define TEGRA_EHCI_UTMIP_SPARE_CFG0_REG 0x834
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#define TEGRA_EHCI_UTMIP_XCVR_CFG1_REG 0x838
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#define TEGRA_EHCI_UTMIP_XCVR_CFG1_TERM_RANGE_ADJ __BITS(21,18)
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#define TEGRA_EHCI_UTMIP_XCVR_CFG1_PDDR_POWERDOWN __BIT(4)
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#define TEGRA_EHCI_UTMIP_XCVR_CFG1_PDCHRP_POWERDOWN __BIT(2)
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#define TEGRA_EHCI_UTMIP_XCVR_CFG1_PDDISC_POWERDOWN __BIT(0)
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#define TEGRA_EHCI_UTMIP_BIAS_CFG1_REG 0x83c
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#define TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_COUNT __BITS(7,3)
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#define TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_POWERDOWN __BIT(0)
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#define TEGRA_EHCI_UTMIP_HSRX_CFG0_REG 0xc08
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#define TEGRA_EHCI_UTMIP_HSRX_CFG0_IDLE_WAIT __BITS(19,15)
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#define TEGRA_EHCI_UTMIP_HSRX_CFG0_ELASTIC_LIMIT __BITS(14,10)
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#define TEGRA_EHCI_UTMIP_HSRX_CFG1_REG 0xc0c
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#define TEGRA_EHCI_UTMIP_HSRX_CFG1_SYNC_START_DLY __BITS(5,1)
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#endif /* _ARM_TEGRA_USBREG_H */
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