179 lines
5.5 KiB
ArmAsm
179 lines
5.5 KiB
ArmAsm
/* $NetBSD: ixm1200_start.S,v 1.3 2008/04/28 20:23:17 martin Exp $ */
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/*
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* Copyright (c) 2002 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Ichiro FUKUHARA and Naoto Shimazaki.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "assym.h"
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#include <arm/asm.h>
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#include <arm/armreg.h>
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#include <arm/arm32/pte.h>
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.section .start,"ax",%progbits
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.global _C_LABEL(ixm1200_start)
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_C_LABEL(ixm1200_start):
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/*
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* Disable IRQ and FIQ
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*/
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mrs r3, cpsr_all
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orr r1, r3, #(I32_bit | F32_bit)
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msr cpsr_all, r1
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/*
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* Setup coprocessor 15.
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*
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* We assume we've been loaded VA == PA, or that the MMU is
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* disabled. We will go ahead and disable the MMU here
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* so that we don't have to worry about flushing caches, etc.
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*/
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/* CONTROL_CP15 */
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mrc p15, 0, r0, c1, c0 ,0 /* read ctrl */
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bic r0, r0, #CPU_CONTROL_MMU_ENABLE
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bic r0, r0, #CPU_CONTROL_AFLT_ENABLE
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orr r0, r0, #CPU_CONTROL_DC_ENABLE
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orr r0, r0, #CPU_CONTROL_WBUF_ENABLE
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bic r0, r0, #CPU_CONTROL_BEND_ENABLE
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orr r0, r0, #CPU_CONTROL_SYST_ENABLE
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bic r0, r0, #CPU_CONTROL_ROM_ENABLE
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orr r0, r0, #CPU_CONTROL_IC_ENABLE
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bic r0, r0, #CPU_CONTROL_VECRELOC
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mcr p15, 0, r0, c1, c0 ,0 /* write ctrl */
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nop
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nop
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nop
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/* TRANSLATION_TABLE_BASE */
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mov r0, #0
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mcr p15, 0, r0, c2, c0 ,0 /* write trans table base */
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/* DOMAIN_ACCESS_CONTROL */
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mov r0, #0x00000001 /* use domain 0 as client */
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mcr p15, 0, r0, c3, c0 ,0 /* write domain */
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/* CACHE_CONTROL_OPERATIONS */
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mrc p15, 0, r0, c7, c7 ,0 /* flush D and I cache */
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mrc p15, 0, r0, c7, c10 ,4 /* drain write buffer */
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/* TLB_OPERATIONS */
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mcr p15, 0, r0, c8, c7 ,0 /* flush D and I TLB */
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/* READ_BUFFER_OPERATIONS */
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mcr p15, 0, r0, c9, c0 ,0 /* flush all entries */
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mcr p15, 0, r0, c9, c0 ,4 /* disable user mode MCR access */
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/* PROCESS_ID_VIRTUAL_ADDR_MAPPING */
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mov r0, #0
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mcr p15, 0, r0, c13, c0 ,0 /* process ID 0
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/* BREAKPOINT_DEBUG_SUPPORT */
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mov r0, #0
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mcr p15, 0, r0, c15, c0 ,0 /* DBAR = 0 */
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mcr p15, 0, r0, c15, c1 ,0 /* DBVR = 0 */
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mcr p15, 0, r0, c15, c2 ,0 /* DBMR = 0 */
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mcr p15, 0, r0, c15, c3 ,0 /* DBCR = 0 (never watch) */
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mcr p15, 0, r0, c15, c8 ,0 /* IBCR = 0 (never watch) */
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/*
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* We want to construct a memory map that maps us
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* VA == PA (SDRAM at 0xc0000000). We create these mappings
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* uncached and unbuffered to be safe.
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*
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* We also want to map the various devices we want to
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* talk to VA == PA during bootstrap.
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*
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* We also want to map the v0xf0000000 == p0x90000000
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* to output eary bootstrup messages to the console.
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*
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* We just use section mappings for all of this to make it easy.
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*
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* We will put the L1 table to do all this at c01fc000
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* where is our KERNEL_TEXT_BASE - sizeof(L1 table).
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*/
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/*
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* Step 1: Map the entire address space VA == PA.
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*/
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ldr r0, Ltable
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mov r1, #(L1_TABLE_SIZE / 4) /* 4096 entry */
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mov r2, #(L1_S_SIZE) /* 1MB / section */
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mov r3, #(L1_S_AP(AP_KRW)) /* kernel read/write */
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orr r3, r3, #(L1_TYPE_S) /* L1 entry is section */
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1:
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str r3, [r0], #4
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add r3, r3, r2
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subs r1, r1, #1
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bgt 1b
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/*
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* Step 2: Map VA 0xf0000000->0xf0100000 to PA 0x90000000->0x90100000.
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*/
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ldr r0, Ltable
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add r0, r0, #(0xf00 * 4) /* offset to 0xf0000000 */
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mov r3, #0x90000000
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add r3, r3, #0x00100000 /* set 0x90100000 to r3 */
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orr r3, r3, #(L1_S_AP(AP_KRW)) /* kernel read/write */
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orr r3, r3, #(L1_TYPE_S) /* L1 entry is section */
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str r3, [r0]
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/* OK! Page table is set up. Give it to the CPU. */
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ldr r0, Ltable
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mcr p15, 0, r0, c2, c0 ,0 /* write trans table base */
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mcr p15, 0, r0, c8, c7 ,0 /* flush D and I TLB */
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/* Get ready to jump to the "real" kernel entry point... */
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ldr r0, Lstart
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/* OK, let's enable the MMU. */
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mrc p15, 0, r1, c1, c0 ,0 /* read ctrl */
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orr r1, r1, #CPU_CONTROL_MMU_ENABLE
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mcr p15, 0, r1, c1, c0 ,0 /* write ctrl */
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nop
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nop
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nop
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/* CPWAIT sequence to make sure the MMU is on... */
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mrc p15, 0, r2, c2, c0, 0 /* arbitrary read of CP15 */
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mov r2, r2 /* force it to complete */
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mov pc, r0 /* leap to kernel entry point! */
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Lstart:
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.word start
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Ltable:
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.word 0xc0200000 - 0x4000 /* our KERNEL_TEXT_BASE - 16KB */
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/* end of ixm1200_start.S */
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