102 lines
3.9 KiB
C
102 lines
3.9 KiB
C
/* $NetBSD: spdmemreg.h,v 1.1 2010/03/24 00:31:41 pgoyette Exp $ */
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/*
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* Copyright (c) 2007 Paul Goyette
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/* possible values for the memory type */
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#define SPDMEM_MEMTYPE_FPM 0x01
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#define SPDMEM_MEMTYPE_EDO 0x02
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#define SPDMEM_MEMTYPE_PIPE_NIBBLE 0x03
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#define SPDMEM_MEMTYPE_SDRAM 0x04
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#define SPDMEM_MEMTYPE_ROM 0x05
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#define SPDMEM_MEMTYPE_DDRSGRAM 0x06
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#define SPDMEM_MEMTYPE_DDRSDRAM 0x07
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#define SPDMEM_MEMTYPE_DDR2SDRAM 0x08
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#define SPDMEM_MEMTYPE_FBDIMM 0x09
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#define SPDMEM_MEMTYPE_FBDIMM_PROBE 0x0A
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#define SPDMEM_MEMTYPE_DDR3SDRAM 0x0B
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#define SPDMEM_MEMTYPE_RAMBUS 0x11
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#define SPDMEM_MEMTYPE_DIRECTRAMBUS 0x01
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/* Encodings of the size used/total byte for certain memory types */
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#define SPDMEM_SPDSIZE_MASK 0x0F /* SPD EEPROM Size */
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#define SPDMEM_SPDLEN_128 0x00 /* SPD EEPROM Sizes */
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#define SPDMEM_SPDLEN_176 0x10
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#define SPDMEM_SPDLEN_256 0x20
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#define SPDMEM_SPDLEN_MASK 0x70 /* Bits 4 - 6 */
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#define SPDMEM_SPDCRC_116 0x80 /* CRC Bytes covered */
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#define SPDMEM_SPDCRC_125 0x00
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#define SPDMEM_SPDCRC_MASK 0x80 /* Bit 7 */
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/* possible values for the supply voltage */
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#define SPDMEM_VOLTAGE_TTL_5V 0x00
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#define SPDMEM_VOLTAGE_TTL_LV 0x01
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#define SPDMEM_VOLTAGE_HSTTL_1_5V 0x02
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#define SPDMEM_VOLTAGE_SSTL_3_3V 0x03
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#define SPDMEM_VOLTAGE_SSTL_2_5V 0x04
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#define SPDMEM_VOLTAGE_SSTL_1_8V 0x05
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/* possible values for module configuration */
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#define SPDMEM_MODCONFIG_PARITY 0x01
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#define SPDMEM_MODCONFIG_ECC 0x02
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/* for DDR2, module configuration is a bit-mask field */
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#define SPDMEM_MODCONFIG_HAS_DATA_PARITY 0x01
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#define SPDMEM_MODCONFIG_HAS_DATA_ECC 0x02
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#define SPDMEM_MODCONFIG_HAS_ADDR_CMD_PARITY 0x04
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/* possible values for the refresh field */
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#define SPDMEM_REFRESH_STD 0x00
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#define SPDMEM_REFRESH_QUARTER 0x01
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#define SPDMEM_REFRESH_HALF 0x02
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#define SPDMEM_REFRESH_TWOX 0x03
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#define SPDMEM_REFRESH_FOURX 0x04
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#define SPDMEM_REFRESH_EIGHTX 0x05
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#define SPDMEM_REFRESH_SELFREFRESH 0x80
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/* superset types */
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#define SPDMEM_SUPERSET_ESDRAM 0x01
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#define SPDMEM_SUPERSET_DDR_ESDRAM 0x02
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#define SPDMEM_SUPERSET_EDO_PEM 0x03
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#define SPDMEM_SUPERSET_SDRAM_PEM 0x04
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/* bit masks for "registered" module attribute */
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#define SPDMEM_SDR_MASK_REG 0x02
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#define SPDMEM_DDR_MASK_REG 0x02
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#define SPDMEM_DDR2_MASK_REG 0x05
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#define SPDMEM_DDR3_TYPE_RDIMM 0x01
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#define SPDMEM_DDR3_TYPE_UDIMM 0x02
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#define SPDMEM_DDR3_TYPE_SODIMM 0x03
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#define SPDMEM_DDR3_TYPE_MICRODIMM 0x04
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#define SPDMEM_DDR3_TYPE_MINI_RDIMM 0x05
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#define SPDMEM_DDR3_TYPE_MINI_UDIMM 0x06
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