119 lines
3.6 KiB
C
119 lines
3.6 KiB
C
/* $NetBSD: ninjaata32var.h,v 1.5 2011/02/21 02:32:00 itohy Exp $ */
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/*
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* Copyright (c) 2006 ITOH Yasufumi.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _NJATA32VAR_H_
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#define _NJATA32VAR_H_
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#define NJATA32NAME(sc) (device_xname(sc->sc_wdcdev.sc_atac.atac_dev))
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/* ??? */
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#define NJATA32_MAX_XFER (64 * 1024)
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/*
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* DMA page
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*/
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/* # device */
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#define NJATA32_NUM_DEV 2
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/* # scatter/gather table entries */
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#define NJATA32_NUM_SG NJATA32_SGT_MAXENTRY
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struct njata32_dma_page {
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/*
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* scatter/gather transfer table
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*/
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struct njata32_sgtable dp_sg[NJATA32_NUM_DEV][NJATA32_NUM_SG];
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};
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#define NJATA32_NCHAN 1 /* only one channel */
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struct njata32_softc {
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struct wdc_softc sc_wdcdev; /* common wdc definitions */
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unsigned sc_flags;
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#define NJATA32_IO_MAPPED 0x00000001
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#define NJATA32_MEM_MAPPED 0x00000002
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#define NJATA32_CMDPG_MAPPED 0x00000004
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unsigned sc_devflags;
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/* interrupt handle */
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void *sc_ih;
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struct ninjaata32_channel { /* per-channel data */
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struct ata_channel ch_ata_channel; /* generic part */
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} sc_ch[NJATA32_NCHAN];
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struct ata_channel *sc_wdc_chanarray[NJATA32_NCHAN];
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struct ata_queue sc_wdc_chqueue;
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struct wdc_regs sc_wdc_regs;
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#define NJATA32_REGT(sc) (sc)->sc_wdc_regs.cmd_iot
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#define NJATA32_REGH(sc) (sc)->sc_wdc_regs.cmd_baseioh
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/* for DMA */
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bus_dma_tag_t sc_dmat;
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struct njata32_dma_page *sc_sgtpg; /* scatter/gather table page */
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#if 0
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bus_addr_t sc_sgt_dma;
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#endif
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bus_dma_segment_t sc_sgt_seg;
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bus_dmamap_t sc_dmamap_sgt;
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int sc_sgt_nsegs;
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int sc_piobm_nsegs;
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uint8_t sc_timing_pio;
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#if 0 /* ATA DMA is currently unused */
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uint8_t sc_timing_dma;
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#endif
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uint8_t sc_atawait;
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/* per-device structure */
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struct njata32_device {
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/* DMA resource */
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struct njata32_sgtable *d_sgt; /* for host */
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bus_addr_t d_sgt_dma; /* for device */
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bus_dmamap_t d_dmamap_xfer;
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unsigned d_flags;
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#define NJATA32_DEV_DMA_MAPPED 0x0001
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#define NJATA32_DEV_DMA_READ 0x0002
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#define NJATA32_DEV_DMA_ATAPI 0x0004
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#define NJATA32_DEV_XFER_INTR 0x0100 /* only for sc_devflags */
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#define NJATA32_DEV_GOT_XFER_INTR 0x0200 /* only for sc_devflags */
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#define NJATA32_DEV_DMA_STARTED 0x8000 /* for diag */
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} sc_dev[NJATA32_NUM_DEV];
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};
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#ifdef _KERNEL
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void njata32_attach(struct njata32_softc *);
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int njata32_detach(struct njata32_softc *, int);
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int njata32_intr(void *);
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#endif
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#endif /* _NJATA32VAR_H_ */
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