243 lines
7.0 KiB
C
243 lines
7.0 KiB
C
/* $NetBSD: atppcvar.h,v 1.12 2011/05/26 02:29:23 jakllsch Exp $ */
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/*-
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* Copyright (c) 2001 Alcove - Nicolas Souchu
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* FreeBSD: src/sys/isa/ppcreg.h,v 1.10.2.4 2001/10/02 05:21:45 nsouch Exp
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*
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*/
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#ifndef __ATPPCVAR_H
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#define __ATPPCVAR_H
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#include <sys/bus.h>
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#include <machine/types.h>
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#include <sys/device.h>
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#include <sys/callout.h>
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#include <sys/mutex.h>
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#include <sys/condvar.h>
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#include <dev/ppbus/ppbus_conf.h>
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/* Maximum time to wait for device response */
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#define MAXBUSYWAIT (5 * (hz))
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/* Poll interval when waiting for device to become ready */
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#define ATPPC_POLL ((hz)/10)
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/* Diagnostic and verbose printing macros */
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#ifdef ATPPC_DEBUG
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extern int atppc_debug;
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#define ATPPC_DPRINTF(arg) if(atppc_debug) printf arg
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#else
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#define ATPPC_DPRINTF(arg)
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#endif
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#ifdef ATPPC_VERBOSE
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extern int atppc_verbose;
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#define ATPPC_VPRINTF(arg) if(atppc_verbose) printf arg
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#else
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#define ATPPC_VPRINTF(arg)
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#endif
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/* Flag used in DMA transfer */
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#define ATPPC_DMA_MODE_READ 0x0
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#define ATPPC_DMA_MODE_WRITE 0x1
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/* Flags passed via config */
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#define ATPPC_FLAG_DISABLE_INTR 0x01
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#define ATPPC_FLAG_DISABLE_DMA 0x02
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/* Single softintr callback entry */
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struct atppc_handler_node {
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void (*func)(void *);
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void *arg;
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SLIST_ENTRY(atppc_handler_node) entries;
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};
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/* Generic structure to hold parallel port chipset info. */
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struct atppc_softc {
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/* Generic device attributes */
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device_t sc_dev;
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kmutex_t sc_lock;
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kcondvar_t sc_out_cv;
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kcondvar_t sc_in_cv;
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/* Machine independent bus infrastructure */
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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bus_dma_tag_t sc_dmat;
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bus_dmamap_t sc_dmapt;
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bus_size_t sc_dma_maxsize;
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/* Child device */
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device_t child;
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/* Opaque handle used for interrupt handler establishment */
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void *sc_ieh;
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/* List of soft interrupts to call */
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SLIST_HEAD(handler_list, atppc_handler_node) sc_handler_listhead;
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/* Input buffer: working pointers, and size in bytes. */
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char * sc_inb;
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char * sc_inbstart;
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u_int32_t sc_inb_nbytes;
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int sc_inerr;
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/* Output buffer pointer, working pointer, and size in bytes. */
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char * sc_outb;
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char * sc_outbstart;
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u_int32_t sc_outb_nbytes;
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int sc_outerr;
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/* DMA functions: setup by bus specific attach code */
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int (*sc_dma_start)(struct atppc_softc *, void *, u_int, u_int8_t);
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int (*sc_dma_finish)(struct atppc_softc *);
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int (*sc_dma_abort)(struct atppc_softc *);
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int (*sc_dma_malloc)(device_t, void **, bus_addr_t *,
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bus_size_t);
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void (*sc_dma_free)(device_t, void **, bus_addr_t *,
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bus_size_t);
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/* Microsequence related members */
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char * sc_ptr; /* microseq current pointer */
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int sc_accum; /* microseq accumulator */
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/* Device attachment state */
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#define ATPPC_ATTACHED 1
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#define ATPPC_NOATTACH 0
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u_int8_t sc_dev_ok;
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/*
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* Hardware capabilities flags: standard mode and nibble mode are
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* assumed to always be available since if they aren't you don't
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* HAVE a parallel port.
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*/
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#define ATPPC_HAS_INTR 0x01 /* Interrupt available */
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#define ATPPC_HAS_DMA 0x02 /* DMA available */
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#define ATPPC_HAS_FIFO 0x04 /* FIFO available */
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#define ATPPC_HAS_PS2 0x08 /* PS2 mode capable */
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#define ATPPC_HAS_ECP 0x10 /* ECP mode available */
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#define ATPPC_HAS_EPP 0x20 /* EPP mode available */
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u_int8_t sc_has; /* Chipset detected capabilities */
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/* Flags specifying mode of chipset operation . */
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#define ATPPC_MODE_STD 0x01 /* Use centronics-compatible mode */
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#define ATPPC_MODE_PS2 0x02 /* Use PS2 mode */
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#define ATPPC_MODE_EPP 0x04 /* Use EPP mode */
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#define ATPPC_MODE_ECP 0x08 /* Use ECP mode */
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#define ATPPC_MODE_NIBBLE 0x10 /* Use nibble mode */
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#define ATPPC_MODE_FAST 0x20 /* Use Fast Centronics mode */
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u_int8_t sc_mode; /* Current operational mode */
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/* Flags which further define chipset operation */
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#define ATPPC_USE_INTR 0x01 /* Use interrupts */
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#define ATPPC_USE_DMA 0x02 /* Use DMA */
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u_int8_t sc_use; /* Capabilities to use */
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/* Parallel Port Chipset model. */
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#define SMC_LIKE 0
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#define SMC_37C665GT 1
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#define SMC_37C666GT 2
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#define NS_PC87332 3
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#define NS_PC87306 4
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#define INTEL_820191AA 5 /* XXX not implemented */
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#define GENERIC 6
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#define WINB_W83877F 7
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#define WINB_W83877AF 8
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#define WINB_UNKNOWN 9
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#define NS_PC87334 10
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#define SMC_37C935 11
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#define NS_PC87303 12
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u_int8_t sc_model; /* chipset model */
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/* EPP mode */
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#define ATPPC_EPP_1_9 0x0
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#define ATPPC_EPP_1_7 0x1
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u_int8_t sc_epp;
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/* Parallel Port Chipset Type. SMC versus GENERIC (others) */
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#define ATPPC_TYPE_SMCLIKE 0
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#define ATPPC_TYPE_GENERIC 1
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u_int8_t sc_type; /* generic or smclike chipset type */
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/* Stored register values after an interrupt occurs */
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u_int8_t sc_ecr_intr;
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u_int8_t sc_ctr_intr;
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u_int8_t sc_str_intr;
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#define ATPPC_IRQ_NONE 0x0
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#define ATPPC_IRQ_nACK 0x1
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#define ATPPC_IRQ_DMA 0x2
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#define ATPPC_IRQ_FIFO 0x4
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#define ATPPC_IRQ_nFAULT 0x8
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u_int8_t sc_irqstat; /* Record irq settings */
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#define ATPPC_DMA_INIT 0x01
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#define ATPPC_DMA_STARTED 0x02
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#define ATPPC_DMA_COMPLETE 0x03
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#define ATPPC_DMA_INTERRUPTED 0x04
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#define ATPPC_DMA_ERROR 0x05
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u_int8_t sc_dmastat; /* Record dma state */
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#define ATPPC_PWORD_MASK 0x30
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#define ATPPC_PWORD_16 0x00
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#define ATPPC_PWORD_8 0x10
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#define ATPPC_PWORD_32 0x20
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u_int8_t sc_pword; /* PWord size: used for FIFO DMA transfers */
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u_int8_t sc_fifo; /* FIFO size */
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/* Indicates number of PWords in FIFO queues that generate interrupt */
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u_int8_t sc_wthr; /* writeIntrThresold */
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u_int8_t sc_rthr; /* readIntrThresold */
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};
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#ifdef _KERNEL
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/* Function prototypes */
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/* Soft config attach/detach routines */
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void atppc_sc_attach(struct atppc_softc *);
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int atppc_sc_detach(struct atppc_softc *, int);
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/* Detection routines */
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int atppc_detect_port(bus_space_tag_t, bus_space_handle_t);
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/* Interrupt handler for atppc device */
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int atppcintr(void *);
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#endif /* _KERNEL */
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#endif /* __ATPPCVAR_H */
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