c339e55881
C5P and later cores (also known as 'ACE', which is part of the VIA PadLock security engine). Ported from OpenBSD. Reviewed on tech-crypto and port-i386, no objections to commiting this.
501 lines
14 KiB
C
501 lines
14 KiB
C
/* $NetBSD: cpu.h,v 1.133 2007/02/17 00:28:25 daniel Exp $ */
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/*-
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)cpu.h 5.4 (Berkeley) 5/9/91
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*/
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#ifndef _I386_CPU_H_
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#define _I386_CPU_H_
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#ifdef _KERNEL
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#if defined(_KERNEL_OPT)
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#include "opt_enhanced_speedstep.h"
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#include "opt_multiprocessor.h"
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#include "opt_math_emulate.h"
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#include "opt_user_ldt.h"
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#include "opt_vm86.h"
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#endif
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/*
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* Definitions unique to i386 cpu support.
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*/
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#include <machine/frame.h>
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#include <machine/segments.h>
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#include <machine/tss.h>
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#include <machine/intrdefs.h>
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#include <x86/cacheinfo.h>
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#include <x86/via_padlock.h>
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#include <sys/device.h>
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#include <sys/lock.h> /* will also get LOCKDEBUG */
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#include <sys/cpu_data.h>
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#include <sys/cc_microtime.h>
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#include <lib/libkern/libkern.h> /* offsetof */
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struct intrsource;
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struct pmap;
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/*
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* a bunch of this belongs in cpuvar.h; move it later..
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*/
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struct cpu_info {
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struct device *ci_dev; /* pointer to our device */
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struct cpu_info *ci_self; /* self-pointer */
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void *ci_self150; /* self + 0x150, see lock_stubs.S */
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void *ci_tlog_base; /* Trap log base */
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int32_t ci_tlog_offset; /* Trap log current offset */
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struct cpu_info *ci_next; /* next cpu */
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/*
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* Public members.
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*/
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struct lwp *ci_curlwp; /* current owner of the processor */
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struct simplelock ci_slock; /* lock on this data structure */
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cpuid_t ci_cpuid; /* our CPU ID */
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u_int ci_apicid; /* our APIC ID */
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struct cpu_data ci_data; /* MI per-cpu data */
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struct cc_microtime_state ci_cc;/* cc_microtime state */
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/*
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* Private members.
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*/
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struct lwp *ci_fpcurlwp; /* current owner of the FPU */
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int ci_fpsaving; /* save in progress */
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volatile uint32_t ci_tlb_ipi_mask;
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struct pmap *ci_pmap; /* current pmap */
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int ci_want_pmapload; /* pmap_load() is needed */
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int ci_tlbstate; /* one of TLBSTATE_ states. see below */
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#define TLBSTATE_VALID 0 /* all user tlbs are valid */
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#define TLBSTATE_LAZY 1 /* tlbs are valid but won't be kept uptodate */
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#define TLBSTATE_STALE 2 /* we might have stale user tlbs */
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struct pcb *ci_curpcb; /* VA of current HW PCB */
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struct pcb *ci_idle_pcb; /* VA of current PCB */
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int ci_idle_tss_sel; /* TSS selector of idle PCB */
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struct intrsource *ci_isources[MAX_INTR_SOURCES];
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volatile int ci_mtx_count; /* Negative count of spin mutexes */
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volatile int ci_mtx_oldspl; /* Old SPL at this ci_idepth */
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/* The following must be aligned for cmpxchg8b. */
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struct {
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uint32_t ipending;
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int ilevel;
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} ci_istate __aligned(8);
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#define ci_ipending ci_istate.ipending
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#define ci_ilevel ci_istate.ilevel
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int ci_idepth;
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uint32_t ci_imask[NIPL];
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uint32_t ci_iunmask[NIPL];
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void * ci_intrstack;
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paddr_t ci_idle_pcb_paddr; /* PA of idle PCB */
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uint32_t ci_flags; /* flags; see below */
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uint32_t ci_ipis; /* interprocessor interrupts pending */
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int sc_apic_version; /* local APIC version */
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int32_t ci_cpuid_level;
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uint32_t ci_signature; /* X86 cpuid type */
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uint32_t ci_feature_flags;/* X86 %edx CPUID feature bits */
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uint32_t ci_feature2_flags;/* X86 %ecx CPUID feature bits */
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uint32_t ci_feature3_flags;/* X86 extended feature bits */
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uint32_t ci_padlock_flags;/* VIA PadLock feature bits */
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uint32_t ci_cpu_class; /* CPU class */
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uint32_t ci_brand_id; /* Intel brand id */
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uint32_t ci_vendor[4]; /* vendor string */
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uint32_t ci_cpu_serial[3]; /* PIII serial number */
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uint64_t ci_tsc_freq; /* cpu cycles/second */
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struct cpu_functions *ci_func; /* start/stop functions */
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void (*cpu_setup)(struct cpu_info *);
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/* proc-dependant init */
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void (*ci_info)(struct cpu_info *);
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int ci_want_resched;
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int ci_astpending;
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struct trapframe *ci_ddb_regs;
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u_int ci_cflush_lsize; /* CFLUSH insn line size */
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struct x86_cache_info ci_cinfo[CAI_COUNT];
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union descriptor *ci_gdt;
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struct i386tss ci_doubleflt_tss;
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struct i386tss ci_ddbipi_tss;
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char *ci_doubleflt_stack;
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char *ci_ddbipi_stack;
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struct evcnt ci_ipi_events[X86_NIPI];
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struct via_padlock ci_vp; /* VIA PadLock private storage */
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};
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/*
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* Processor flag notes: The "primary" CPU has certain MI-defined
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* roles (mostly relating to hardclock handling); we distinguish
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* betwen the processor which booted us, and the processor currently
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* holding the "primary" role just to give us the flexibility later to
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* change primaries should we be sufficiently twisted.
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*/
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#define CPUF_BSP 0x0001 /* CPU is the original BSP */
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#define CPUF_AP 0x0002 /* CPU is an AP */
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#define CPUF_SP 0x0004 /* CPU is only processor */
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#define CPUF_PRIMARY 0x0008 /* CPU is active primary processor */
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#define CPUF_APIC_CD 0x0010 /* CPU has apic configured */
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#define CPUF_PRESENT 0x1000 /* CPU is present */
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#define CPUF_RUNNING 0x2000 /* CPU is running */
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#define CPUF_PAUSE 0x4000 /* CPU is paused in DDB */
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#define CPUF_GO 0x8000 /* CPU should start running */
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/*
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* We statically allocate the CPU info for the primary CPU (or,
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* the only CPU on uniprocessors), and the primary CPU is the
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* first CPU on the CPU info list.
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*/
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extern struct cpu_info cpu_info_primary;
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extern struct cpu_info *cpu_info_list;
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#define CPU_INFO_ITERATOR int
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#define CPU_INFO_FOREACH(cii, ci) cii = 0, ci = cpu_info_list; \
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ci != NULL; ci = ci->ci_next
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#if defined(MULTIPROCESSOR)
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#define X86_MAXPROCS 32 /* because we use a bitmask */
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#define CPU_STARTUP(_ci) ((_ci)->ci_func->start(_ci))
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#define CPU_STOP(_ci) ((_ci)->ci_func->stop(_ci))
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#define CPU_START_CLEANUP(_ci) ((_ci)->ci_func->cleanup(_ci))
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static struct cpu_info *curcpu(void);
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__inline static struct cpu_info * __attribute__((__unused__))
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curcpu()
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{
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struct cpu_info *ci;
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__asm volatile("movl %%fs:%1, %0" :
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"=r" (ci) :
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"m"
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(*(struct cpu_info * const *)offsetof(struct cpu_info, ci_self)));
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return ci;
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}
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#define cpu_number() (curcpu()->ci_cpuid)
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#define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY)
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#define aston(l) ((l)->l_md.md_astpending = 1)
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extern struct cpu_info *cpu_info[X86_MAXPROCS];
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void cpu_boot_secondary_processors(void);
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void cpu_init_idle_pcbs(void);
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#else /* !MULTIPROCESSOR */
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#define X86_MAXPROCS 1
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#define curcpu() (&cpu_info_primary)
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/*
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* definitions of cpu-dependent requirements
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* referenced in generic code
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*/
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#define cpu_number() 0
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#define CPU_IS_PRIMARY(ci) 1
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#define aston(l) ((l)->l_md.md_astpending = 1)
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#endif /* MULTIPROCESSOR */
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/*
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* Preempt the current process if in interrupt from user mode,
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* or after the current trap/syscall if in system mode.
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*/
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extern void cpu_need_resched(struct cpu_info *);
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extern uint32_t cpus_attached;
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#define curpcb curcpu()->ci_curpcb
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#define curlwp curcpu()->ci_curlwp
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/*
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* Arguments to hardclock, softclock and statclock
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* encapsulate the previous machine state in an opaque
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* clockframe; for now, use generic intrframe.
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*/
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struct clockframe {
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struct intrframe cf_if;
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};
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#define CLKF_USERMODE(frame) USERMODE((frame)->cf_if.if_cs, (frame)->cf_if.if_eflags)
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#define CLKF_PC(frame) ((frame)->cf_if.if_eip)
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#define CLKF_INTR(frame) (curcpu()->ci_idepth > 0)
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/*
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* This is used during profiling to integrate system time. It can safely
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* assume that the process is resident.
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*/
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#define LWP_PC(l) ((l)->l_md.md_regs->tf_eip)
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/*
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* Give a profiling tick to the current process when the user profiling
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* buffer pages are invalid. On the i386, request an ast to send us
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* through trap(), marking the proc as needing a profiling tick.
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*/
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extern void cpu_need_proftick(struct lwp *l);
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/*
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* Notify the LWP l that it has a signal pending, process as soon as
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* possible.
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*/
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extern void cpu_signotify(struct lwp *);
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/*
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* We need a machine-independent name for this.
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*/
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extern void (*delay_func)(int);
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struct timeval;
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#define DELAY(x) (*delay_func)(x)
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#define delay(x) (*delay_func)(x)
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/*
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* pull in #defines for kinds of processors
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*/
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#include <machine/cputypes.h>
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struct cpu_nocpuid_nameclass {
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int cpu_vendor;
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const char *cpu_vendorname;
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const char *cpu_name;
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int cpu_class;
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void (*cpu_setup)(struct cpu_info *);
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void (*cpu_cacheinfo)(struct cpu_info *);
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void (*cpu_info)(struct cpu_info *);
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};
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struct cpu_cpuid_nameclass {
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const char *cpu_id;
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int cpu_vendor;
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const char *cpu_vendorname;
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struct cpu_cpuid_family {
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int cpu_class;
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const char *cpu_models[CPU_MAXMODEL+2];
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void (*cpu_setup)(struct cpu_info *);
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void (*cpu_probe)(struct cpu_info *);
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void (*cpu_info)(struct cpu_info *);
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} cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1];
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};
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extern int biosbasemem;
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extern int biosextmem;
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extern unsigned int cpu_feature;
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extern unsigned int cpu_feature2;
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extern unsigned int cpu_feature_padlock;
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extern int cpu;
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extern int cpu_class;
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extern char cpu_brand_string[];
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extern const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[];
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extern const struct cpu_cpuid_nameclass i386_cpuid_cpus[];
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extern int i386_use_fxsave;
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extern int i386_has_sse;
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extern int i386_has_sse2;
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/* machdep.c */
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void dumpconf(void);
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int cpu_maxproc(void);
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void cpu_reset(void);
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void i386_init_pcb_tss_ldt(struct cpu_info *);
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void i386_proc0_tss_ldt_init(void);
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/* identcpu.c */
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#ifdef ENHANCED_SPEEDSTEP
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extern int bus_clock;
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#endif
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extern int tmx86_has_longrun;
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extern u_int crusoe_longrun;
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extern u_int crusoe_frequency;
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extern u_int crusoe_voltage;
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extern u_int crusoe_percentage;
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extern u_int tmx86_set_longrun_mode(u_int);
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void tmx86_get_longrun_status_all(void);
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u_int tmx86_get_longrun_mode(void);
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void identifycpu(struct cpu_info *);
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/* vm_machdep.c */
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void cpu_proc_fork(struct proc *, struct proc *);
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/* locore.s */
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struct region_descriptor;
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void lgdt(struct region_descriptor *);
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void fillw(short, void *, size_t);
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struct pcb;
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void savectx(struct pcb *);
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void proc_trampoline(void);
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/* clock.c */
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void initrtclock(u_long);
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void startrtclock(void);
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void i8254_delay(int);
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void i8254_microtime(struct timeval *);
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void i8254_initclocks(void);
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/* cpu.c */
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void cpu_probe_features(struct cpu_info *);
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/* npx.c */
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void npxsave_lwp(struct lwp *, int);
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void npxsave_cpu(struct cpu_info *, int);
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/* vm_machdep.c */
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int kvtop(caddr_t);
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#ifdef MATH_EMULATE
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/* math_emulate.c */
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int math_emulate(struct trapframe *, ksiginfo_t *);
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#endif
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#ifdef USER_LDT
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/* sys_machdep.h */
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int i386_get_ldt(struct lwp *, void *, register_t *);
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int i386_set_ldt(struct lwp *, void *, register_t *);
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#endif
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/* isa_machdep.c */
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void isa_defaultirq(void);
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int isa_nmi(void);
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#ifdef VM86
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/* vm86.c */
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void vm86_gpfault(struct lwp *, int);
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#endif /* VM86 */
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/* consinit.c */
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void kgdb_port_init(void);
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/* bus_machdep.c */
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void x86_bus_space_init(void);
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void x86_bus_space_mallocok(void);
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#include <machine/psl.h> /* Must be after struct cpu_info declaration */
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/* est.c */
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void est_init(struct cpu_info *, int);
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#endif /* _KERNEL */
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/*
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* CTL_MACHDEP definitions.
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*/
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#define CPU_CONSDEV 1 /* dev_t: console terminal device */
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#define CPU_BIOSBASEMEM 2 /* int: bios-reported base mem (K) */
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#define CPU_BIOSEXTMEM 3 /* int: bios-reported ext. mem (K) */
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#define CPU_NKPDE 4 /* int: number of kernel PDEs */
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#define CPU_BOOTED_KERNEL 5 /* string: booted kernel name */
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#define CPU_DISKINFO 6 /* struct disklist *:
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* disk geometry information */
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#define CPU_FPU_PRESENT 7 /* int: FPU is present */
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#define CPU_OSFXSR 8 /* int: OS uses FXSAVE/FXRSTOR */
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#define CPU_SSE 9 /* int: OS/CPU supports SSE */
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#define CPU_SSE2 10 /* int: OS/CPU supports SSE2 */
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#define CPU_TMLR_MODE 11 /* int: longrun mode
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* 0: minimum frequency
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* 1: economy
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* 2: performance
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* 3: maximum frequency
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*/
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#define CPU_TMLR_FREQUENCY 12 /* int: current frequency */
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#define CPU_TMLR_VOLTAGE 13 /* int: curret voltage */
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#define CPU_TMLR_PERCENTAGE 14 /* int: current clock percentage */
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#define CPU_MAXID 15 /* number of valid machdep ids */
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#define CTL_MACHDEP_NAMES { \
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{ 0, 0 }, \
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{ "console_device", CTLTYPE_STRUCT }, \
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{ "biosbasemem", CTLTYPE_INT }, \
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{ "biosextmem", CTLTYPE_INT }, \
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{ "nkpde", CTLTYPE_INT }, \
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{ "booted_kernel", CTLTYPE_STRING }, \
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{ "diskinfo", CTLTYPE_STRUCT }, \
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{ "fpu_present", CTLTYPE_INT }, \
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{ "osfxsr", CTLTYPE_INT }, \
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{ "sse", CTLTYPE_INT }, \
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{ "sse2", CTLTYPE_INT }, \
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{ "tm_longrun_mode", CTLTYPE_INT }, \
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{ "tm_longrun_frequency", CTLTYPE_INT }, \
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{ "tm_longrun_voltage", CTLTYPE_INT }, \
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{ "tm_longrun_percentage", CTLTYPE_INT }, \
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}
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/*
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* Structure for CPU_DISKINFO sysctl call.
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* XXX this should be somewhere else.
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*/
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#define MAX_BIOSDISKS 16
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struct disklist {
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int dl_nbiosdisks; /* number of bios disks */
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struct biosdisk_info {
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int bi_dev; /* BIOS device # (0x80 ..) */
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int bi_cyl; /* cylinders on disk */
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int bi_head; /* heads per track */
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int bi_sec; /* sectors per track */
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uint64_t bi_lbasecs; /* total sec. (iff ext13) */
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#define BIFLAG_INVALID 0x01
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#define BIFLAG_EXTINT13 0x02
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int bi_flags;
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} dl_biosdisks[MAX_BIOSDISKS];
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int dl_nnativedisks; /* number of native disks */
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struct nativedisk_info {
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char ni_devname[16]; /* native device name */
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int ni_nmatches; /* # of matches w/ BIOS */
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int ni_biosmatches[MAX_BIOSDISKS]; /* indices in dl_biosdisks */
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} dl_nativedisks[1]; /* actually longer */
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};
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#endif /* !_I386_CPU_H_ */
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