478 lines
12 KiB
C
478 lines
12 KiB
C
/* $NetBSD: if_atw_cardbus.c,v 1.3 2003/11/16 09:02:42 dyoung Exp $ */
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/*-
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* Copyright (c) 1999, 2000, 2003 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center. This code was adapted for the ADMtek ADM8211
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* by David Young.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* CardBus bus front-end for the ADMtek ADM8211 802.11 MAC/BBP driver.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: if_atw_cardbus.c,v 1.3 2003/11/16 09:02:42 dyoung Exp $");
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#include "opt_inet.h"
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#include "opt_ns.h"
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#include "bpfilter.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/mbuf.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/socket.h>
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#include <sys/ioctl.h>
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#include <sys/errno.h>
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#include <sys/device.h>
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#include <machine/endian.h>
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#include <net/if.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/if_ether.h>
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#include <net80211/ieee80211_compat.h>
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#include <net80211/ieee80211_radiotap.h>
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#include <net80211/ieee80211_var.h>
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#if NBPFILTER > 0
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#include <net/bpf.h>
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#endif
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#ifdef INET
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#include <netinet/in.h>
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#include <netinet/if_inarp.h>
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#endif
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#ifdef NS
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#include <netns/ns.h>
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#include <netns/ns_if.h>
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#endif
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <dev/mii/miivar.h>
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#include <dev/mii/mii_bitbang.h>
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#include <dev/ic/atwreg.h>
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#include <dev/ic/atwvar.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/cardbus/cardbusvar.h>
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#include <dev/cardbus/cardbusdevs.h>
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/*
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* PCI configuration space registers used by the ADM8211.
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*/
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#define ATW_PCI_IOBA 0x10 /* i/o mapped base */
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#define ATW_PCI_MMBA 0x14 /* memory mapped base */
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struct atw_cardbus_softc {
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struct atw_softc sc_atw; /* real ADM8211 softc */
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/* CardBus-specific goo. */
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void *sc_ih; /* interrupt handle */
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cardbus_devfunc_t sc_ct; /* our CardBus devfuncs */
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cardbustag_t sc_tag; /* our CardBus tag */
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int sc_csr; /* CSR bits */
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bus_size_t sc_mapsize; /* the size of mapped bus space
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region */
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int sc_cben; /* CardBus enables */
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int sc_bar_reg; /* which BAR to use */
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pcireg_t sc_bar_val; /* value of the BAR */
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int sc_intrline; /* interrupt line */
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};
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int atw_cardbus_match __P((struct device *, struct cfdata *, void *));
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void atw_cardbus_attach __P((struct device *, struct device *, void *));
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int atw_cardbus_detach __P((struct device *, int));
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CFATTACH_DECL(atw_cardbus, sizeof(struct atw_cardbus_softc),
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atw_cardbus_match, atw_cardbus_attach, atw_cardbus_detach, atw_activate);
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void atw_cardbus_setup __P((struct atw_cardbus_softc *));
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int atw_cardbus_enable __P((struct atw_softc *));
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void atw_cardbus_disable __P((struct atw_softc *));
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void atw_cardbus_power __P((struct atw_softc *, int));
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static void atw_cardbus_intr_ack(struct atw_softc *);
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const struct atw_cardbus_product *atw_cardbus_lookup
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__P((const struct cardbus_attach_args *));
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const struct atw_cardbus_product {
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u_int32_t acp_vendor; /* PCI vendor ID */
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u_int32_t acp_product; /* PCI product ID */
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const char *acp_product_name;
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} atw_cardbus_products[] = {
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{ PCI_VENDOR_ADMTEK, PCI_PRODUCT_ADMTEK_ADM8211,
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"ADMtek ADM8211 802.11 MAC/BBP" },
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{ 0, 0, NULL },
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};
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const struct atw_cardbus_product *
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atw_cardbus_lookup(ca)
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const struct cardbus_attach_args *ca;
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{
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const struct atw_cardbus_product *acp;
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for (acp = atw_cardbus_products;
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acp->acp_product_name != NULL;
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acp++) {
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if (PCI_VENDOR(ca->ca_id) == acp->acp_vendor &&
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PCI_PRODUCT(ca->ca_id) == acp->acp_product)
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return (acp);
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}
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return (NULL);
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}
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int
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atw_cardbus_match(parent, match, aux)
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struct device *parent;
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struct cfdata *match;
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void *aux;
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{
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struct cardbus_attach_args *ca = aux;
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if (atw_cardbus_lookup(ca) != NULL)
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return (1);
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return (0);
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}
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void
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atw_cardbus_attach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct atw_cardbus_softc *csc = (void *)self;
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struct atw_softc *sc = &csc->sc_atw;
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struct cardbus_attach_args *ca = aux;
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cardbus_devfunc_t ct = ca->ca_ct;
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const struct atw_cardbus_product *acp;
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bus_addr_t adr;
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int rev;
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sc->sc_dmat = ca->ca_dmat;
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csc->sc_ct = ct;
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csc->sc_tag = ca->ca_tag;
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acp = atw_cardbus_lookup(ca);
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if (acp == NULL) {
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printf("\n");
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panic("atw_cardbus_attach: impossible");
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}
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/*
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* Power management hooks.
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*/
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sc->sc_enable = atw_cardbus_enable;
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sc->sc_disable = atw_cardbus_disable;
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sc->sc_power = atw_cardbus_power;
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sc->sc_intr_ack = atw_cardbus_intr_ack;
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/* Get revision info. */
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rev = PCI_REVISION(ca->ca_class);
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printf(": %s\n", acp->acp_product_name);
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#if 0
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printf("%s: pass %d.%d signature %08x\n", sc->sc_dev.dv_xname,
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(rev >> 4) & 0xf, rev & 0xf,
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cardbus_conf_read(ct->ct_cc, ct->ct_cf, csc->sc_tag, 0x80));
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#endif
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/*
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* Map the device.
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*/
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csc->sc_csr = CARDBUS_COMMAND_MASTER_ENABLE;
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if (Cardbus_mapreg_map(ct, ATW_PCI_MMBA,
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CARDBUS_MAPREG_TYPE_MEM, 0, &sc->sc_st, &sc->sc_sh, &adr,
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&csc->sc_mapsize) == 0) {
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#if 0
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printf("%s: atw_cardbus_attach mapped %d bytes mem space\n",
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sc->sc_dev.dv_xname, csc->sc_mapsize);
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#endif
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#if rbus
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#else
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(*ct->ct_cf->cardbus_mem_open)(cc, 0, adr, adr+csc->sc_mapsize);
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#endif
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csc->sc_cben = CARDBUS_MEM_ENABLE;
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csc->sc_csr |= CARDBUS_COMMAND_MEM_ENABLE;
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csc->sc_bar_reg = ATW_PCI_MMBA;
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csc->sc_bar_val = adr | CARDBUS_MAPREG_TYPE_MEM;
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} else if (Cardbus_mapreg_map(ct, ATW_PCI_IOBA,
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CARDBUS_MAPREG_TYPE_IO, 0, &sc->sc_st, &sc->sc_sh, &adr,
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&csc->sc_mapsize) == 0) {
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#if 0
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printf("%s: atw_cardbus_attach mapped %d bytes I/O space\n",
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sc->sc_dev.dv_xname, csc->sc_mapsize);
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#endif
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#if rbus
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#else
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(*ct->ct_cf->cardbus_io_open)(cc, 0, adr, adr+csc->sc_mapsize);
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#endif
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csc->sc_cben = CARDBUS_IO_ENABLE;
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csc->sc_csr |= CARDBUS_COMMAND_IO_ENABLE;
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csc->sc_bar_reg = ATW_PCI_IOBA;
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csc->sc_bar_val = adr | CARDBUS_MAPREG_TYPE_IO;
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} else {
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printf("%s: unable to map device registers\n",
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sc->sc_dev.dv_xname);
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return;
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}
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/*
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* Bring the chip out of powersave mode and initialize the
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* configuration registers.
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*/
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atw_cardbus_setup(csc);
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/* Remember which interrupt line. */
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csc->sc_intrline = ca->ca_intrline;
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printf("%s: interrupting at %d\n", sc->sc_dev.dv_xname,
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csc->sc_intrline);
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#if 0
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/*
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* The CardBus cards will make it to store-and-forward mode as
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* soon as you put them under any kind of load, so just start
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* out there.
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*/
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sc->sc_txthresh = 3; /* TBD name constant */
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#endif
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/*
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* Finish off the attach.
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*/
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atw_attach(sc);
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ATW_WRITE(sc, ATW_FER, ATW_FER_INTR);
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/*
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* Power down the socket.
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*/
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Cardbus_function_disable(csc->sc_ct);
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}
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static void
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atw_cardbus_intr_ack(sc)
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struct atw_softc *sc;
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{
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ATW_WRITE(sc, ATW_FER, ATW_FER_INTR);
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}
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int
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atw_cardbus_detach(self, flags)
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struct device *self;
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int flags;
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{
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struct atw_cardbus_softc *csc = (void *)self;
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struct atw_softc *sc = &csc->sc_atw;
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struct cardbus_devfunc *ct = csc->sc_ct;
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int rv;
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#if defined(DIAGNOSTIC)
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if (ct == NULL)
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panic("%s: data structure lacks", sc->sc_dev.dv_xname);
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#endif
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rv = atw_detach(sc);
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if (rv)
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return (rv);
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/*
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* Unhook the interrupt handler.
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*/
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if (csc->sc_ih != NULL)
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cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, csc->sc_ih);
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/*
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* Release bus space and close window.
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*/
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if (csc->sc_bar_reg != 0)
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Cardbus_mapreg_unmap(ct, csc->sc_bar_reg,
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sc->sc_st, sc->sc_sh, csc->sc_mapsize);
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return (0);
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}
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int
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atw_cardbus_enable(sc)
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struct atw_softc *sc;
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{
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struct atw_cardbus_softc *csc = (void *) sc;
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cardbus_devfunc_t ct = csc->sc_ct;
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cardbus_chipset_tag_t cc = ct->ct_cc;
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cardbus_function_tag_t cf = ct->ct_cf;
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/*
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* Power on the socket.
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*/
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Cardbus_function_enable(ct);
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/*
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* Set up the PCI configuration registers.
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*/
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atw_cardbus_setup(csc);
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/*
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* Map and establish the interrupt.
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*/
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csc->sc_ih = cardbus_intr_establish(cc, cf, csc->sc_intrline, IPL_NET,
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atw_intr, sc);
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if (csc->sc_ih == NULL) {
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printf("%s: unable to establish interrupt at %d\n",
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sc->sc_dev.dv_xname, csc->sc_intrline);
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Cardbus_function_disable(csc->sc_ct);
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return (1);
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}
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return (0);
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}
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void
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atw_cardbus_disable(sc)
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struct atw_softc *sc;
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{
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struct atw_cardbus_softc *csc = (void *) sc;
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cardbus_devfunc_t ct = csc->sc_ct;
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cardbus_chipset_tag_t cc = ct->ct_cc;
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cardbus_function_tag_t cf = ct->ct_cf;
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/* Unhook the interrupt handler. */
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cardbus_intr_disestablish(cc, cf, csc->sc_ih);
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csc->sc_ih = NULL;
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/* Power down the socket. */
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Cardbus_function_disable(ct);
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}
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void
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atw_cardbus_power(sc, why)
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struct atw_softc *sc;
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int why;
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{
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struct atw_cardbus_softc *csc = (void *) sc;
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printf("%s: atw_cardbus_power\n", sc->sc_dev.dv_xname);
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if (why == PWR_RESUME) {
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/*
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* Give the PCI configuration registers a kick
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* in the head.
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*/
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#ifdef DIAGNOSTIC
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if (ATW_IS_ENABLED(sc) == 0)
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panic("atw_cardbus_power");
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#endif
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atw_cardbus_setup(csc);
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}
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}
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void
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atw_cardbus_setup(csc)
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struct atw_cardbus_softc *csc;
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{
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struct atw_softc *sc = &csc->sc_atw;
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cardbus_devfunc_t ct = csc->sc_ct;
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cardbus_chipset_tag_t cc = ct->ct_cc;
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cardbus_function_tag_t cf = ct->ct_cf;
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pcireg_t reg;
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int pmreg;
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if (cardbus_get_capability(cc, cf, csc->sc_tag,
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PCI_CAP_PWRMGMT, &pmreg, 0)) {
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reg = cardbus_conf_read(cc, cf, csc->sc_tag, pmreg + 4) & 0x03;
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#if 1 /* XXX Probably not right for CardBus. */
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if (reg == 3) {
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/*
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* The card has lost all configuration data in
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* this state, so punt.
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*/
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printf("%s: unable to wake up from power state D3\n",
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sc->sc_dev.dv_xname);
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return;
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}
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#endif
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if (reg != 0) {
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printf("%s: waking up from power state D%d\n",
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sc->sc_dev.dv_xname, reg);
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cardbus_conf_write(cc, cf, csc->sc_tag,
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pmreg + 4, 0);
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}
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}
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/* Make sure the right access type is on the CardBus bridge. */
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(*ct->ct_cf->cardbus_ctrl)(cc, csc->sc_cben);
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(*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE);
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/* Program the BAR. */
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cardbus_conf_write(cc, cf, csc->sc_tag, csc->sc_bar_reg,
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csc->sc_bar_val);
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/* Enable the appropriate bits in the PCI CSR. */
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reg = cardbus_conf_read(cc, cf, csc->sc_tag,
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CARDBUS_COMMAND_STATUS_REG);
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reg &= ~(CARDBUS_COMMAND_IO_ENABLE|CARDBUS_COMMAND_MEM_ENABLE);
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reg |= csc->sc_csr;
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cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_COMMAND_STATUS_REG,
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reg);
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/*
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* Make sure the latency timer is set to some reasonable
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* value.
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*/
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reg = cardbus_conf_read(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG);
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if (CARDBUS_LATTIMER(reg) < 0x20) {
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reg &= ~(CARDBUS_LATTIMER_MASK << CARDBUS_LATTIMER_SHIFT);
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reg |= (0x20 << CARDBUS_LATTIMER_SHIFT);
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cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG, reg);
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}
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}
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