103 lines
2.9 KiB
C
103 lines
2.9 KiB
C
/* $NetBSD: cacheops_20.h,v 1.9 2008/04/28 20:23:26 martin Exp $ */
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/*-
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* Copyright (c) 1997 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Leo Weppelman
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Invalidate entire TLB.
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*/
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static __inline void __attribute__((__unused__))
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TBIA_20(void)
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{
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__asm volatile (" pflusha");
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}
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/*
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* Invalidate any TLB entry for given VA (TB Invalidate Single)
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*/
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static __inline void __attribute__((__unused__))
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TBIS_20(vaddr_t va)
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{
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__asm volatile (" pflushs #0,#0,%0@" : : "a" (va) );
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}
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/*
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* Invalidate supervisor side of TLB
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*/
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static __inline void __attribute__((__unused__))
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TBIAS_20(void)
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{
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__asm volatile (" pflushs #4,#4");
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}
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/*
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* Invalidate user side of TLB
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*/
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static __inline void __attribute__((__unused__))
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TBIAU_20(void)
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{
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__asm volatile (" pflushs #0,#4;");
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}
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/*
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* Invalidate instruction cache
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*/
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static __inline void __attribute__((__unused__))
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ICIA_20(void)
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{
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__asm volatile (" movc %0,%%cacr;" : : "d" (IC_CLEAR));
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}
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static __inline void __attribute__((__unused__))
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ICPA_20(void)
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{
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__asm volatile (" movc %0,%%cacr;" : : "d" (IC_CLEAR));
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}
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/*
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* Invalidate data cache.
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* NOTE: we do not flush 68030/20 on-chip cache as there are no aliasing
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* problems with DC_WA. The only cases we have to worry about are context
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* switch and TLB changes, both of which are handled "in-line" in resume
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* and TBI*.
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*/
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#define DCIA_20()
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#define DCIS_20()
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#define DCIU_20()
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#define DCIAS_20(va)
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#define DCFA_20()
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#define DCPA_20()
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static __inline void __attribute__((__unused__))
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PCIA_20(void)
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{
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__asm volatile (" movc %0,%%cacr;" : : "d" (DC_CLEAR));
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}
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