91 lines
3.5 KiB
C
91 lines
3.5 KiB
C
/* $NetBSD: cpuregs.h,v 1.1 2001/10/16 16:31:35 uch Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by UCHIYAMA Yasushi.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/* R5900 has Enable Interrupt Enable bit. */
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#undef MIPS_SR_INT_IE
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#define MIPS_SR_INT_IE 0x00010001 /* EIE + IE */
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#undef COP0_SYNC
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#define COP0_SYNC sync.p
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/*
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* R5900 has INT5,1,0 only don't support software interrupt
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* MIPS_SOFT_INT_MASK_1 and MIPS_SOFT_INT_MASK_1 are emulated by kernel.
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*/
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#undef MIPS_INT_MASK
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#define MIPS_INT_MASK 0x0c00
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#undef MIPS_HARD_INT_MASK
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#define MIPS_HARD_INT_MASK 0x0c00
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#undef MIPS_COP_0_LLADDR
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#undef MIPS_COP_0_WATCH_LO
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#undef MIPS_COP_0_WATCH_HI
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#undef MIPS_COP_0_TLB_XCONTEXT
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#undef MIPS_COP_0_ECC
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#undef MIPS_COP_0_CACHE_ERR
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#undef MIPS_COP_0_DESAVE
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/* Exception vector */
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#define R5900_TLB_REFIL_EXC_VEC 0x80000000
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#define R5900_COUNTER_EXC_VEC 0x80000080
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#define R5900_DEBUG_EXC_VEC 0x80000100
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#define R5900_COMMON_EXC_VEC 0x80000180
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#define R5900_INTERRUPT_EXC_VEC 0x80000200
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/* Cache */
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#define R5900_C_SIZE_I 16384
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#define R5900_C_SIZE_D 8192
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#define R5900_C_LSIZE_I 64
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#define R5900_C_LSIZE_D 64
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#define R5900_C_IINV_I 0x07 /* INDEX INVALIDATE */
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#define R5900_C_IWBINV_D 0x14 /* INDEX WRITE BACK INVALIDATE */
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#define R5900_C_ILTG_D 0x10 /* INDEX LOAD TAG */
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#define R5900_C_ISTG_D 0x12 /* INDEX STORE TAG */
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#define R5900_C_IINV_D 0x16 /* INDEX INVALIDATE */
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#define R5900_C_HINV_D 0x1a /* HIT INVALIDATE */
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#define R5900_C_HWBINV_D 0x18 /* HIT WRITEBACK INVALIDATE */
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#define R5900_C_ILDT_D 0x11 /* INDEX LOAD DATA */
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#define R5900_C_ISDT_D 0x13 /* INDEX STORE DATA */
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#define R5900_C_HWBWOINV_D 0x1c /* HIT WRITEBACK W/O INVALIDATE */
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/* MMU R5900 support 32bit-mode only */
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#define dmtc0 mtc0
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#define dmfc0 mfc0
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