1019 lines
24 KiB
C
1019 lines
24 KiB
C
/* $NetBSD: oea_machdep.c,v 1.64 2012/02/16 07:59:46 matt Exp $ */
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/*
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* Copyright (C) 2002 Matt Thomas
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* Copyright (C) 1995, 1996 Wolfgang Solfrank.
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* Copyright (C) 1995, 1996 TooLs GmbH.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by TooLs GmbH.
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* 4. The name of TooLs GmbH may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: oea_machdep.c,v 1.64 2012/02/16 07:59:46 matt Exp $");
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#include "opt_ppcarch.h"
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#include "opt_compat_netbsd.h"
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#include "opt_ddb.h"
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#include "opt_kgdb.h"
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#include "opt_ipkdb.h"
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#include "opt_multiprocessor.h"
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#include "opt_altivec.h"
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#include <sys/param.h>
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#include <sys/buf.h>
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#include <sys/boot_flag.h>
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#include <sys/exec.h>
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#include <sys/kernel.h>
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#include <sys/mbuf.h>
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#include <sys/mount.h>
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#include <sys/msgbuf.h>
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#include <sys/proc.h>
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#include <sys/reboot.h>
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#include <sys/syscallargs.h>
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#include <sys/syslog.h>
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#include <sys/systm.h>
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#include <uvm/uvm_extern.h>
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#ifdef DDB
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#include <powerpc/db_machdep.h>
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#include <ddb/db_extern.h>
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#endif
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#ifdef KGDB
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#include <sys/kgdb.h>
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#endif
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#ifdef IPKDB
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#include <ipkdb/ipkdb.h>
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#endif
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#include <machine/powerpc.h>
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#include <powerpc/trap.h>
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#include <powerpc/spr.h>
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#include <powerpc/pte.h>
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#include <powerpc/altivec.h>
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#include <powerpc/pcb.h>
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#include <powerpc/oea/bat.h>
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#include <powerpc/oea/cpufeat.h>
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#include <powerpc/oea/spr.h>
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#include <powerpc/oea/sr_601.h>
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char machine[] = MACHINE; /* from <machine/param.h> */
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char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */
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struct vm_map *phys_map = NULL;
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/*
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* Global variables used here and there
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*/
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static void trap0(void *);
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/* XXXSL: The battable is not initialized to non-zero for PPC_OEA64 and PPC_OEA64_BRIDGE */
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struct bat battable[BAT_VA2IDX(0xffffffff)+1];
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register_t iosrtable[16]; /* I/O segments, for kernel_pmap setup */
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#ifndef MSGBUFADDR
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paddr_t msgbuf_paddr;
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#endif
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extern int dsitrap_fix_dbat4[];
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extern int dsitrap_fix_dbat5[];
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extern int dsitrap_fix_dbat6[];
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extern int dsitrap_fix_dbat7[];
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void
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oea_init(void (*handler)(void))
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{
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extern int trapcode[], trapsize[];
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extern int sctrap[], scsize[];
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extern int alitrap[], alisize[];
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extern int dsitrap[], dsisize[];
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extern int trapstart[], trapend[];
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#ifdef PPC_OEA601
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extern int dsi601trap[], dsi601size[];
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#endif
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extern int decrint[], decrsize[];
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extern int tlbimiss[], tlbimsize[];
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extern int tlbdlmiss[], tlbdlmsize[];
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extern int tlbdsmiss[], tlbdsmsize[];
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#if defined(DDB) || defined(KGDB)
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extern int ddblow[], ddbsize[];
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#endif
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#ifdef IPKDB
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extern int ipkdblow[], ipkdbsize[];
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#endif
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#ifdef ALTIVEC
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register_t msr;
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#endif
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uintptr_t exc, exc_base;
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#if defined(ALTIVEC) || defined(PPC_OEA)
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register_t scratch;
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#endif
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unsigned int cpuvers;
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size_t size;
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struct cpu_info * const ci = &cpu_info[0];
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#ifdef PPC_HIGH_VEC
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exc_base = EXC_HIGHVEC;
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#else
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exc_base = 0;
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#endif
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KASSERT(mfspr(SPR_SPRG0) == (uintptr_t)ci);
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cpuvers = mfpvr() >> 16;
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/*
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* Initialize proc0 and current pcb and pmap pointers.
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*/
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(void) ci;
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KASSERT(ci != NULL);
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KASSERT(curcpu() == ci);
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KASSERT(lwp0.l_cpu == ci);
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curpcb = lwp_getpcb(&lwp0);
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memset(curpcb, 0, sizeof(struct pcb));
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#ifdef ALTIVEC
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/*
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* Initialize the vectors with NaNs
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*/
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for (scratch = 0; scratch < 32; scratch++) {
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curpcb->pcb_vr.vreg[scratch][0] = 0x7FFFDEAD;
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curpcb->pcb_vr.vreg[scratch][1] = 0x7FFFDEAD;
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curpcb->pcb_vr.vreg[scratch][2] = 0x7FFFDEAD;
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curpcb->pcb_vr.vreg[scratch][3] = 0x7FFFDEAD;
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}
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#endif
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curpm = curpcb->pcb_pm = pmap_kernel();
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/*
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* Cause a PGM trap if we branch to 0.
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*
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* XXX GCC4.1 complains about memset on address zero, so
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* don't use the builtin.
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*/
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#undef memset
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memset(0, 0, 0x100);
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/*
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* Set up trap vectors. Don't assume vectors are on 0x100.
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*/
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for (exc = exc_base; exc <= exc_base + EXC_LAST; exc += 0x100) {
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switch (exc - exc_base) {
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default:
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size = (size_t)trapsize;
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memcpy((void *)exc, trapcode, size);
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break;
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#if 0
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case EXC_EXI:
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/*
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* This one is (potentially) installed during autoconf
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*/
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break;
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#endif
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case EXC_SC:
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size = (size_t)scsize;
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memcpy((void *)exc, sctrap, size);
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break;
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case EXC_ALI:
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size = (size_t)alisize;
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memcpy((void *)exc, alitrap, size);
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break;
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case EXC_DSI:
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#ifdef PPC_OEA601
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if (cpuvers == MPC601) {
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size = (size_t)dsi601size;
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memcpy((void *)exc, dsi601trap, size);
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break;
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} else
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#endif /* PPC_OEA601 */
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if (oeacpufeat & OEACPU_NOBAT) {
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size = (size_t)alisize;
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memcpy((void *)exc, alitrap, size);
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} else {
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size = (size_t)dsisize;
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memcpy((void *)exc, dsitrap, size);
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}
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break;
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case EXC_DECR:
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size = (size_t)decrsize;
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memcpy((void *)exc, decrint, size);
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break;
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case EXC_IMISS:
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size = (size_t)tlbimsize;
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memcpy((void *)exc, tlbimiss, size);
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break;
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case EXC_DLMISS:
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size = (size_t)tlbdlmsize;
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memcpy((void *)exc, tlbdlmiss, size);
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break;
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case EXC_DSMISS:
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size = (size_t)tlbdsmsize;
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memcpy((void *)exc, tlbdsmiss, size);
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break;
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case EXC_PERF:
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size = (size_t)trapsize;
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memcpy((void *)exc, trapcode, size);
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memcpy((void *)(exc_base + EXC_VEC), trapcode, size);
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break;
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#if defined(DDB) || defined(IPKDB) || defined(KGDB)
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case EXC_RUNMODETRC:
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#ifdef PPC_OEA601
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if (cpuvers != MPC601) {
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#endif
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size = (size_t)trapsize;
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memcpy((void *)exc, trapcode, size);
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break;
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#ifdef PPC_OEA601
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}
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/* FALLTHROUGH */
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#endif
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case EXC_PGM:
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case EXC_TRC:
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case EXC_BPT:
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#if defined(DDB) || defined(KGDB)
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size = (size_t)ddbsize;
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memcpy((void *)exc, ddblow, size);
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#if defined(IPKDB)
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#error "cannot enable IPKDB with DDB or KGDB"
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#endif
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#else
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size = (size_t)ipkdbsize;
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memcpy((void *)exc, ipkdblow, size);
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#endif
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break;
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#endif /* DDB || IPKDB || KGDB */
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}
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#if 0
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exc += roundup(size, 32);
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#endif
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}
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/*
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* Install a branch absolute to trap0 to force a panic.
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*/
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if ((uintptr_t)trap0 < 0x2000000) {
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*(uint32_t *) 0 = 0x7c6802a6;
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*(uint32_t *) 4 = 0x48000002 | (uintptr_t) trap0;
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}
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/*
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* Get the cache sizes because install_extint calls __syncicache.
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*/
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cpu_probe_cache();
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#define MxSPR_MASK 0x7c1fffff
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#define MFSPR_MQ 0x7c0002a6
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#define MTSPR_MQ 0x7c0003a6
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#define MTSPR_IBAT0L 0x7c1183a6
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#define MTSPR_IBAT1L 0x7c1383a6
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#define NOP 0x60000000
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#define B 0x48000000
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#define TLBSYNC 0x7c00046c
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#define SYNC 0x7c0004ac
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#ifdef ALTIVEC
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#define MFSPR_VRSAVE 0x7c0042a6
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#define MTSPR_VRSAVE 0x7c0043a6
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/*
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* Try to set the VEC bit in the MSR. If it doesn't get set, we are
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* not on a AltiVec capable processor.
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*/
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__asm volatile (
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"mfmsr %0; oris %1,%0,%2@h; mtmsr %1; isync; "
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"mfmsr %1; mtmsr %0; isync"
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: "=r"(msr), "=r"(scratch)
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: "J"(PSL_VEC));
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/*
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* If we aren't on an AltiVec capable processor, we need to zap any of
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* the sequences we save/restore the VRSAVE SPR into NOPs.
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*/
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if (scratch & PSL_VEC) {
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cpu_altivec = 1;
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} else {
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int *ip = trapstart;
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for (; ip < trapend; ip++) {
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if ((ip[0] & MxSPR_MASK) == MFSPR_VRSAVE) {
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ip[0] = NOP; /* mfspr */
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ip[1] = NOP; /* stw */
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} else if ((ip[0] & MxSPR_MASK) == MTSPR_VRSAVE) {
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ip[-1] = NOP; /* lwz */
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ip[0] = NOP; /* mtspr */
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}
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}
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}
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#endif
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/* XXX It would seem like this code could be elided ifndef 601, but
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* doing so breaks my power3 machine.
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*/
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/*
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* If we aren't on a MPC601 processor, we need to zap any of the
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* sequences we save/restore the MQ SPR into NOPs, and skip over the
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* sequences where we zap/restore BAT registers on kernel exit/entry.
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*/
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if (cpuvers != MPC601) {
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int *ip = trapstart;
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for (; ip < trapend; ip++) {
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if ((ip[0] & MxSPR_MASK) == MFSPR_MQ) {
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ip[0] = NOP; /* mfspr */
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ip[1] = NOP; /* stw */
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} else if ((ip[0] & MxSPR_MASK) == MTSPR_MQ) {
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ip[-1] = NOP; /* lwz */
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ip[0] = NOP; /* mtspr */
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} else if ((ip[0] & MxSPR_MASK) == MTSPR_IBAT0L) {
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if ((ip[1] & MxSPR_MASK) == MTSPR_IBAT1L)
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ip[-1] = B | 0x14; /* li */
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else
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ip[-4] = B | 0x24; /* lis */
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}
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}
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}
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/*
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* Sync the changed instructions.
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*/
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__syncicache((void *) trapstart,
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(uintptr_t) trapend - (uintptr_t) trapstart);
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__syncicache(dsitrap_fix_dbat4, 16);
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__syncicache(dsitrap_fix_dbat7, 8);
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#ifdef PPC_OEA601
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/*
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* If we are on a MPC601 processor, we need to zap any tlbsync
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* instructions into sync. This differs from the above in
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* examing all kernel text, as opposed to just the exception handling.
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* We sync the icache on every instruction found since there are
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* only very few of them.
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*/
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if (cpuvers == MPC601) {
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extern int kernel_text[], etext[];
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int *ip;
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for (ip = kernel_text; ip < etext; ip++)
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if (*ip == TLBSYNC) {
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*ip = SYNC;
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__syncicache(ip, sizeof(*ip));
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}
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}
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#endif /* PPC_OEA601 */
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/*
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* Configure a PSL user mask matching this processor.
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*/
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cpu_psluserset = PSL_EE | PSL_PR | PSL_ME | PSL_IR | PSL_DR | PSL_RI;
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cpu_pslusermod = PSL_FP | PSL_FE0 | PSL_FE1 | PSL_LE | PSL_SE | PSL_BE;
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#ifdef PPC_OEA601
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if (cpuvers == MPC601) {
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cpu_psluserset &= PSL_601_MASK;
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cpu_pslusermod &= PSL_601_MASK;
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}
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#endif
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#ifdef ALTIVEC
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if (cpu_altivec)
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cpu_pslusermod |= PSL_VEC;
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#endif
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#ifdef PPC_HIGH_VEC
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cpu_psluserset |= PSL_IP; /* XXX ok? */
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#endif
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/*
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* external interrupt handler install
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*/
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if (handler)
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oea_install_extint(handler);
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__syncicache((void *)exc_base, EXC_LAST + 0x100);
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/*
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* Now enable translation (and machine checks/recoverable interrupts).
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*/
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#ifdef PPC_OEA
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__asm volatile ("sync; mfmsr %0; ori %0,%0,%1; mtmsr %0; isync"
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: "=r"(scratch)
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: "K"(PSL_IR|PSL_DR|PSL_ME|PSL_RI));
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#endif
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/*
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* Let's take all the indirect calls via our stubs and patch
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* them to be direct calls.
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*/
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cpu_fixup_stubs();
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KASSERT(curcpu() == ci);
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}
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#ifdef PPC_OEA601
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void
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mpc601_ioseg_add(paddr_t pa, register_t len)
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{
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const u_int i = pa >> ADDR_SR_SHFT;
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if (len != BAT_BL_256M)
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panic("mpc601_ioseg_add: len != 256M");
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/*
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* Translate into an I/O segment, load it, and stash away for use
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* in pmap_bootstrap().
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*/
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iosrtable[i] = SR601(SR601_Ks, SR601_BUID_MEMFORCED, 0, i);
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__asm volatile ("mtsrin %0,%1"
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:: "r"(iosrtable[i]),
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"r"(pa));
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}
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#endif /* PPC_OEA601 */
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#if defined (PPC_OEA) || defined (PPC_OEA64_BRIDGE)
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#define DBAT_SET(n, batl, batu) \
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do { \
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mtspr(SPR_DBAT##n##L, (batl)); \
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mtspr(SPR_DBAT##n##U, (batu)); \
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} while (/*CONSTCOND*/ 0)
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#define DBAT_RESET(n) DBAT_SET(n, 0, 0)
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#define DBATU_GET(n) mfspr(SPR_DBAT##n##U)
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#define IBAT_SET(n, batl, batu) \
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do { \
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mtspr(SPR_IBAT##n##L, (batl)); \
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mtspr(SPR_IBAT##n##U, (batu)); \
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} while (/*CONSTCOND*/ 0)
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#define IBAT_RESET(n) IBAT_SET(n, 0, 0)
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void
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oea_iobat_add(paddr_t pa, register_t len)
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{
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static int z = 1;
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const u_int n = BAT_BL_TO_SIZE(len) / BAT_BL_TO_SIZE(BAT_BL_8M);
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const u_int i = BAT_VA2IDX(pa) & -n; /* in case pa was in the middle */
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const int after_bat3 = (oeacpufeat & OEACPU_HIGHBAT) ? 4 : 8;
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KASSERT(len >= BAT_BL_8M);
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/*
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* If the caller wanted a bigger BAT than the hardware supports,
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* split it into smaller BATs.
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*/
|
|
if (len > BAT_BL_256M && (oeacpufeat & OEACPU_XBSEN) == 0) {
|
|
u_int xn = BAT_BL_TO_SIZE(len) >> 28;
|
|
while (xn-- > 0) {
|
|
oea_iobat_add(pa, BAT_BL_256M);
|
|
pa += 0x10000000;
|
|
}
|
|
return;
|
|
}
|
|
|
|
const register_t batl = BATL(pa, BAT_I|BAT_G, BAT_PP_RW);
|
|
const register_t batu = BATU(pa, len, BAT_Vs);
|
|
|
|
for (u_int j = 0; j < n; j++) {
|
|
battable[i + j].batl = batl;
|
|
battable[i + j].batu = batu;
|
|
}
|
|
|
|
/*
|
|
* Let's start loading the BAT registers.
|
|
*/
|
|
switch (z) {
|
|
case 1:
|
|
DBAT_SET(1, batl, batu);
|
|
z = 2;
|
|
break;
|
|
case 2:
|
|
DBAT_SET(2, batl, batu);
|
|
z = 3;
|
|
break;
|
|
case 3:
|
|
DBAT_SET(3, batl, batu);
|
|
z = after_bat3; /* no highbat, skip to end */
|
|
break;
|
|
case 4:
|
|
DBAT_SET(4, batl, batu);
|
|
z = 5;
|
|
break;
|
|
case 5:
|
|
DBAT_SET(5, batl, batu);
|
|
z = 6;
|
|
break;
|
|
case 6:
|
|
DBAT_SET(6, batl, batu);
|
|
z = 7;
|
|
break;
|
|
case 7:
|
|
DBAT_SET(7, batl, batu);
|
|
z = 8;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
void
|
|
oea_iobat_remove(paddr_t pa)
|
|
{
|
|
const u_int i = BAT_VA2IDX(pa);
|
|
|
|
if (!BAT_VA_MATCH_P(battable[i].batu, pa) ||
|
|
!BAT_VALID_P(battable[i].batu, PSL_PR))
|
|
return;
|
|
const int n =
|
|
__SHIFTOUT(battable[i].batu, (BAT_XBL|BAT_BL) & ~BAT_BL_8M) + 1;
|
|
KASSERT((n & (n-1)) == 0); /* power of 2 */
|
|
KASSERT((i & (n-1)) == 0); /* multiple of n */
|
|
|
|
memset(&battable[i], 0, n*sizeof(battable[0]));
|
|
|
|
const int maxbat = oeacpufeat & OEACPU_HIGHBAT ? 8 : 4;
|
|
for (u_int k = 1 ; k < maxbat; k++) {
|
|
register_t batu;
|
|
switch (k) {
|
|
case 1:
|
|
batu = DBATU_GET(1);
|
|
if (BAT_VA_MATCH_P(batu, pa) &&
|
|
BAT_VALID_P(batu, PSL_PR))
|
|
DBAT_RESET(1);
|
|
break;
|
|
case 2:
|
|
batu = DBATU_GET(2);
|
|
if (BAT_VA_MATCH_P(batu, pa) &&
|
|
BAT_VALID_P(batu, PSL_PR))
|
|
DBAT_RESET(2);
|
|
break;
|
|
case 3:
|
|
batu = DBATU_GET(3);
|
|
if (BAT_VA_MATCH_P(batu, pa) &&
|
|
BAT_VALID_P(batu, PSL_PR))
|
|
DBAT_RESET(3);
|
|
break;
|
|
case 4:
|
|
batu = DBATU_GET(4);
|
|
if (BAT_VA_MATCH_P(batu, pa) &&
|
|
BAT_VALID_P(batu, PSL_PR))
|
|
DBAT_RESET(4);
|
|
break;
|
|
case 5:
|
|
batu = DBATU_GET(5);
|
|
if (BAT_VA_MATCH_P(batu, pa) &&
|
|
BAT_VALID_P(batu, PSL_PR))
|
|
DBAT_RESET(5);
|
|
break;
|
|
case 6:
|
|
batu = DBATU_GET(6);
|
|
if (BAT_VA_MATCH_P(batu, pa) &&
|
|
BAT_VALID_P(batu, PSL_PR))
|
|
DBAT_RESET(6);
|
|
break;
|
|
case 7:
|
|
batu = DBATU_GET(7);
|
|
if (BAT_VA_MATCH_P(batu, pa) &&
|
|
BAT_VALID_P(batu, PSL_PR))
|
|
DBAT_RESET(7);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
oea_batinit(paddr_t pa, ...)
|
|
{
|
|
struct mem_region *allmem, *availmem, *mp;
|
|
unsigned int cpuvers;
|
|
register_t msr = mfmsr();
|
|
va_list ap;
|
|
|
|
cpuvers = mfpvr() >> 16;
|
|
|
|
/*
|
|
* we need to call this before zapping BATs so OF calls work
|
|
*/
|
|
mem_regions(&allmem, &availmem);
|
|
|
|
/*
|
|
* Initialize BAT registers to unmapped to not generate
|
|
* overlapping mappings below.
|
|
*
|
|
* The 601's implementation differs in the Valid bit being situated
|
|
* in the lower BAT register, and in being a unified BAT only whose
|
|
* four entries are accessed through the IBAT[0-3] SPRs.
|
|
*
|
|
* Also, while the 601 does distinguish between supervisor/user
|
|
* protection keys, it does _not_ distinguish between validity in
|
|
* supervisor/user mode.
|
|
*/
|
|
if ((msr & (PSL_IR|PSL_DR)) == 0) {
|
|
#ifdef PPC_OEA601
|
|
if (cpuvers == MPC601) {
|
|
__asm volatile ("mtibatl 0,%0" :: "r"(0));
|
|
__asm volatile ("mtibatl 1,%0" :: "r"(0));
|
|
__asm volatile ("mtibatl 2,%0" :: "r"(0));
|
|
__asm volatile ("mtibatl 3,%0" :: "r"(0));
|
|
} else
|
|
#endif /* PPC_OEA601 */
|
|
{
|
|
DBAT_RESET(0); IBAT_RESET(0);
|
|
DBAT_RESET(1); IBAT_RESET(1);
|
|
DBAT_RESET(2); IBAT_RESET(2);
|
|
DBAT_RESET(3); IBAT_RESET(3);
|
|
if (oeacpufeat & OEACPU_HIGHBAT) {
|
|
DBAT_RESET(4); IBAT_RESET(4);
|
|
DBAT_RESET(5); IBAT_RESET(5);
|
|
DBAT_RESET(6); IBAT_RESET(6);
|
|
DBAT_RESET(7); IBAT_RESET(7);
|
|
|
|
/*
|
|
* Change the first instruction to branch to
|
|
* dsitrap_fix_dbat6
|
|
*/
|
|
dsitrap_fix_dbat4[0] &= ~0xfffc;
|
|
dsitrap_fix_dbat4[0]
|
|
+= (uintptr_t)dsitrap_fix_dbat6
|
|
- (uintptr_t)&dsitrap_fix_dbat4[0];
|
|
|
|
/*
|
|
* Change the second instruction to branch to
|
|
* dsitrap_fix_dbat5 if bit 30 (aka bit 1) is
|
|
* true.
|
|
*/
|
|
dsitrap_fix_dbat4[1] = 0x419e0000
|
|
+ (uintptr_t)dsitrap_fix_dbat5
|
|
- (uintptr_t)&dsitrap_fix_dbat4[1];
|
|
|
|
/*
|
|
* Change it to load dbat4 instead of dbat2
|
|
*/
|
|
dsitrap_fix_dbat4[2] = 0x7fd88ba6;
|
|
dsitrap_fix_dbat4[3] = 0x7ff98ba6;
|
|
|
|
/*
|
|
* Change it to load dbat7 instead of dbat3
|
|
*/
|
|
dsitrap_fix_dbat7[0] = 0x7fde8ba6;
|
|
dsitrap_fix_dbat7[1] = 0x7fff8ba6;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Set up BAT to map physical memory
|
|
*/
|
|
#ifdef PPC_OEA601
|
|
if (cpuvers == MPC601) {
|
|
int i;
|
|
|
|
/*
|
|
* Set up battable to map the lowest 256 MB area.
|
|
* Map the lowest 32 MB area via BAT[0-3];
|
|
* BAT[01] are fixed, BAT[23] are floating.
|
|
*/
|
|
for (i = 0; i < 32; i++) {
|
|
battable[i].batl = BATL601(i << 23,
|
|
BAT601_BSM_8M, BAT601_V);
|
|
battable[i].batu = BATU601(i << 23,
|
|
BAT601_M, BAT601_Ku, BAT601_PP_NONE);
|
|
}
|
|
__asm volatile ("mtibatu 0,%1; mtibatl 0,%0"
|
|
:: "r"(battable[0x00000000 >> 23].batl),
|
|
"r"(battable[0x00000000 >> 23].batu));
|
|
__asm volatile ("mtibatu 1,%1; mtibatl 1,%0"
|
|
:: "r"(battable[0x00800000 >> 23].batl),
|
|
"r"(battable[0x00800000 >> 23].batu));
|
|
__asm volatile ("mtibatu 2,%1; mtibatl 2,%0"
|
|
:: "r"(battable[0x01000000 >> 23].batl),
|
|
"r"(battable[0x01000000 >> 23].batu));
|
|
__asm volatile ("mtibatu 3,%1; mtibatl 3,%0"
|
|
:: "r"(battable[0x01800000 >> 23].batl),
|
|
"r"(battable[0x01800000 >> 23].batu));
|
|
}
|
|
#endif /* PPC_OEA601 */
|
|
|
|
/*
|
|
* Now setup other fixed bat registers
|
|
*
|
|
* Note that we still run in real mode, and the BAT
|
|
* registers were cleared above.
|
|
*/
|
|
|
|
va_start(ap, pa);
|
|
|
|
/*
|
|
* Add any I/O BATs specificed;
|
|
* use I/O segments on the BAT-starved 601.
|
|
*/
|
|
#ifdef PPC_OEA601
|
|
if (cpuvers == MPC601) {
|
|
while (pa != 0) {
|
|
register_t len = va_arg(ap, register_t);
|
|
mpc601_ioseg_add(pa, len);
|
|
pa = va_arg(ap, paddr_t);
|
|
}
|
|
} else
|
|
#endif
|
|
{
|
|
while (pa != 0) {
|
|
register_t len = va_arg(ap, register_t);
|
|
oea_iobat_add(pa, len);
|
|
pa = va_arg(ap, paddr_t);
|
|
}
|
|
}
|
|
|
|
va_end(ap);
|
|
|
|
/*
|
|
* Set up battable to map all RAM regions.
|
|
*/
|
|
#ifdef PPC_OEA601
|
|
if (cpuvers == MPC601) {
|
|
for (mp = allmem; mp->size; mp++) {
|
|
paddr_t paddr = mp->start & 0xff800000;
|
|
paddr_t end = mp->start + mp->size;
|
|
|
|
do {
|
|
u_int ix = paddr >> 23;
|
|
|
|
battable[ix].batl =
|
|
BATL601(paddr, BAT601_BSM_8M, BAT601_V);
|
|
battable[ix].batu =
|
|
BATU601(paddr, BAT601_M, BAT601_Ku, BAT601_PP_NONE);
|
|
paddr += (1 << 23);
|
|
} while (paddr < end);
|
|
}
|
|
} else
|
|
#endif
|
|
{
|
|
const register_t bat_inc = BAT_IDX2VA(1);
|
|
for (mp = allmem; mp->size; mp++) {
|
|
paddr_t paddr = mp->start & -bat_inc;
|
|
paddr_t end = roundup2(mp->start + mp->size, bat_inc);
|
|
|
|
/*
|
|
* If the next entries are adjacent, merge them
|
|
* into this one
|
|
*/
|
|
while (mp[1].size && end == (mp[1].start & -bat_inc)) {
|
|
mp++;
|
|
end = roundup2(mp->start + mp->size, bat_inc);
|
|
}
|
|
|
|
while (paddr < end) {
|
|
register_t bl = (oeacpufeat & OEACPU_XBSEN
|
|
? BAT_BL_2G
|
|
: BAT_BL_256M);
|
|
psize_t size = BAT_BL_TO_SIZE(bl);
|
|
u_int n = BAT_VA2IDX(size);
|
|
u_int i = BAT_VA2IDX(paddr);
|
|
|
|
while ((paddr & (size - 1))
|
|
|| paddr + size > end) {
|
|
size >>= 1;
|
|
bl = (bl >> 1) & (BAT_XBL|BAT_BL);
|
|
n >>= 1;
|
|
}
|
|
|
|
KASSERT(size >= bat_inc);
|
|
KASSERT(n >= 1);
|
|
KASSERT(bl >= BAT_BL_8M);
|
|
|
|
register_t batl = BATL(paddr, BAT_M, BAT_PP_RW);
|
|
register_t batu = BATU(paddr, bl, BAT_Vs);
|
|
|
|
for (; n-- > 0; i++) {
|
|
battable[i].batl = batl;
|
|
battable[i].batu = batu;
|
|
}
|
|
paddr += size;
|
|
}
|
|
}
|
|
/*
|
|
* Set up BAT0 to only map the lowest area.
|
|
*/
|
|
__asm volatile ("mtibatl 0,%0; mtibatu 0,%1;"
|
|
"mtdbatl 0,%0; mtdbatu 0,%1;"
|
|
:: "r"(battable[0].batl), "r"(battable[0].batu));
|
|
}
|
|
}
|
|
#endif /* PPC_OEA || PPC_OEA64_BRIDGE */
|
|
|
|
void
|
|
oea_install_extint(void (*handler)(void))
|
|
{
|
|
extern int extint[], extsize[];
|
|
extern int extint_call[];
|
|
uintptr_t offset = (uintptr_t)handler - (uintptr_t)extint_call;
|
|
int omsr, msr;
|
|
|
|
#ifdef DIAGNOSTIC
|
|
if (offset > 0x1ffffff)
|
|
panic("install_extint: %p too far away (%#lx)", handler,
|
|
(unsigned long) offset);
|
|
#endif
|
|
__asm volatile ("mfmsr %0; andi. %1,%0,%2; mtmsr %1"
|
|
: "=r" (omsr), "=r" (msr)
|
|
: "K" ((u_short)~PSL_EE));
|
|
extint_call[0] = (extint_call[0] & 0xfc000003) | offset;
|
|
__syncicache((void *)extint_call, sizeof extint_call[0]);
|
|
#ifdef PPC_HIGH_VEC
|
|
memcpy((void *)(EXC_HIGHVEC + EXC_EXI), extint, (size_t)extsize);
|
|
__syncicache((void *)(EXC_HIGHVEC + EXC_EXI), (int)extsize);
|
|
#else
|
|
memcpy((void *)EXC_EXI, extint, (size_t)extsize);
|
|
__syncicache((void *)EXC_EXI, (int)extsize);
|
|
#endif
|
|
__asm volatile ("mtmsr %0" :: "r"(omsr));
|
|
}
|
|
|
|
/*
|
|
* Machine dependent startup code.
|
|
*/
|
|
void
|
|
oea_startup(const char *model)
|
|
{
|
|
uintptr_t sz;
|
|
void *v;
|
|
vaddr_t minaddr, maxaddr;
|
|
char pbuf[9];
|
|
|
|
KASSERT(curcpu() != NULL);
|
|
KASSERT(lwp0.l_cpu != NULL);
|
|
KASSERT(curcpu()->ci_idepth == -1);
|
|
|
|
sz = round_page(MSGBUFSIZE);
|
|
#ifdef MSGBUFADDR
|
|
v = (void *) MSGBUFADDR;
|
|
#else
|
|
/*
|
|
* If the msgbuf is not in segment 0, allocate KVA for it and access
|
|
* it via mapped pages. [This prevents unneeded BAT switches.]
|
|
*/
|
|
v = (void *) msgbuf_paddr;
|
|
if (msgbuf_paddr + sz > SEGMENT_LENGTH) {
|
|
u_int i;
|
|
|
|
minaddr = 0;
|
|
if (uvm_map(kernel_map, &minaddr, sz,
|
|
NULL, UVM_UNKNOWN_OFFSET, 0,
|
|
UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE,
|
|
UVM_INH_NONE, UVM_ADV_NORMAL, 0)) != 0)
|
|
panic("startup: cannot allocate VM for msgbuf");
|
|
v = (void *)minaddr;
|
|
for (i = 0; i < sz; i += PAGE_SIZE) {
|
|
pmap_kenter_pa(minaddr + i, msgbuf_paddr + i,
|
|
VM_PROT_READ|VM_PROT_WRITE, 0);
|
|
}
|
|
pmap_update(pmap_kernel());
|
|
}
|
|
#endif
|
|
initmsgbuf(v, sz);
|
|
|
|
printf("%s%s", copyright, version);
|
|
if (model != NULL)
|
|
printf("Model: %s\n", model);
|
|
cpu_identify(NULL, 0);
|
|
|
|
format_bytes(pbuf, sizeof(pbuf), ctob((u_int)physmem));
|
|
printf("total memory = %s\n", pbuf);
|
|
|
|
/*
|
|
* Allocate away the pages that map to 0xDEA[CDE]xxxx. Do this after
|
|
* the bufpages are allocated in case they overlap since it's not
|
|
* fatal if we can't allocate these.
|
|
*/
|
|
if (KERNEL_SR == 13 || KERNEL2_SR == 14) {
|
|
int error;
|
|
minaddr = 0xDEAC0000;
|
|
error = uvm_map(kernel_map, &minaddr, 0x30000,
|
|
NULL, UVM_UNKNOWN_OFFSET, 0,
|
|
UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, UVM_INH_NONE,
|
|
UVM_ADV_NORMAL, UVM_FLAG_FIXED));
|
|
if (error != 0 || minaddr != 0xDEAC0000)
|
|
printf("oea_startup: failed to allocate DEAD "
|
|
"ZONE: error=%d\n", error);
|
|
}
|
|
|
|
minaddr = 0;
|
|
|
|
/*
|
|
* Allocate a submap for physio
|
|
*/
|
|
phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr,
|
|
VM_PHYS_SIZE, 0, false, NULL);
|
|
|
|
format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free));
|
|
printf("avail memory = %s\n", pbuf);
|
|
}
|
|
|
|
/*
|
|
* Crash dump handling.
|
|
*/
|
|
|
|
void
|
|
oea_dumpsys(void)
|
|
{
|
|
printf("dumpsys: TBD\n");
|
|
}
|
|
|
|
/*
|
|
* Convert kernel VA to physical address
|
|
*/
|
|
paddr_t
|
|
kvtop(void *addr)
|
|
{
|
|
vaddr_t va;
|
|
paddr_t pa;
|
|
uintptr_t off;
|
|
extern char end[];
|
|
|
|
if (addr < (void *)end)
|
|
return (paddr_t)addr;
|
|
|
|
va = trunc_page((vaddr_t)addr);
|
|
off = (uintptr_t)addr - va;
|
|
|
|
if (pmap_extract(pmap_kernel(), va, &pa) == false) {
|
|
/*printf("kvtop: zero page frame (va=0x%x)\n", addr);*/
|
|
return (paddr_t)addr;
|
|
}
|
|
|
|
return(pa + off);
|
|
}
|
|
|
|
/*
|
|
* Allocate vm space and mapin the I/O address
|
|
*/
|
|
void *
|
|
mapiodev(paddr_t pa, psize_t len, bool prefetchable)
|
|
{
|
|
paddr_t faddr;
|
|
vaddr_t taddr, va;
|
|
int off;
|
|
|
|
faddr = trunc_page(pa);
|
|
off = pa - faddr;
|
|
len = round_page(off + len);
|
|
va = taddr = uvm_km_alloc(kernel_map, len, 0, UVM_KMF_VAONLY);
|
|
|
|
if (va == 0)
|
|
return NULL;
|
|
|
|
for (; len > 0; len -= PAGE_SIZE) {
|
|
pmap_kenter_pa(taddr, faddr, VM_PROT_READ | VM_PROT_WRITE,
|
|
(prefetchable ? PMAP_MD_PREFETCHABLE : PMAP_NOCACHE));
|
|
faddr += PAGE_SIZE;
|
|
taddr += PAGE_SIZE;
|
|
}
|
|
pmap_update(pmap_kernel());
|
|
return (void *)(va + off);
|
|
}
|
|
|
|
void
|
|
unmapiodev(vaddr_t va, vsize_t len)
|
|
{
|
|
paddr_t faddr;
|
|
|
|
if (! va)
|
|
return;
|
|
|
|
faddr = trunc_page(va);
|
|
len = round_page(va - faddr + len);
|
|
|
|
pmap_kremove(faddr, len);
|
|
pmap_update(pmap_kernel());
|
|
uvm_km_free(kernel_map, faddr, len, UVM_KMF_VAONLY);
|
|
}
|
|
|
|
void
|
|
trap0(void *lr)
|
|
{
|
|
panic("call to null-ptr from %p", lr);
|
|
}
|