510 lines
20 KiB
C
510 lines
20 KiB
C
/* $NetBSD: if_wmreg.h,v 1.1 2002/03/28 04:54:35 thorpej Exp $ */
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/*
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* Copyright (c) 2001 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Register description for the Intel i82452 (``Wiseman''),
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* i82543 (``Livengood''), and i82544 (``Cordova'') Gigabit
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* Ethernet chips.
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*/
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/*
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* The wiseman supports 64-bit PCI addressing. This structure
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* describes the address in descriptors.
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*/
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typedef struct wiseman_addr {
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uint32_t wa_low; /* low-order 32 bits */
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uint32_t wa_high; /* high-order 32 bits */
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} __attribute__((__packed__)) wiseman_addr_t;
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/*
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* The Wiseman receive descriptor.
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*
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* The receive descriptor ring must be aligned to a 4K boundary,
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* and there must be an even multiple of 8 descriptors in the ring.
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*/
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typedef struct wiseman_rxdesc {
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wiseman_addr_t wrx_addr; /* buffer address */
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uint16_t wrx_len; /* buffer length */
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uint16_t wrx_cksum; /* checksum (starting at PCSS) */
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uint8_t wrx_status; /* Rx status */
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uint8_t wrx_errors; /* Rx errors */
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uint16_t wrx_special; /* special field (VLAN, etc.) */
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} __attribute__((__packed__)) wiseman_rxdesc_t;
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/* wrx_status bits */
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#define WRX_ST_DD (1U << 0) /* descriptor done */
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#define WRX_ST_EOP (1U << 1) /* end of packet */
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#define WRX_ST_ISXM (1U << 2) /* ignore checksum indication */
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#define WRX_ST_VP (1U << 3) /* VLAN packet */
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#define WRX_ST_BPDU (1U << 4) /* ??? */
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#define WRX_ST_TCPCS (1U << 5) /* TCP checksum performed */
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#define WRX_ST_IPCS (1U << 6) /* IP checksum performed */
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#define WRX_ST_PIF (1U << 7) /* passed in-exact filter */
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/* wrx_error bits */
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#define WRX_ER_CE (1U << 0) /* CRC error */
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#define WRX_ER_SE (1U << 1) /* symbol error */
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#define WRX_ER_SEQ (1U << 2) /* sequence error */
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#define WRX_ER_ICE (1U << 3) /* ??? */
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#define WRX_ER_CXE (1U << 4) /* carrier extension error */
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#define WRX_ER_TCPE (1U << 5) /* TCP checksum error */
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#define WRX_ER_IPE (1U << 6) /* IP checksum error */
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#define WRX_ER_RXE (1U << 7) /* Rx data error */
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/* wrx_special field for VLAN packets */
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#define WRX_VLAN_ID(x) ((x) & 0x0fff) /* VLAN identifier */
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#define WRX_VLAN_CFI (1U << 12) /* Canonical Form Indicator */
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#define WRX_VLAN_PRI(x) (((x) >> 13) & 7)/* VLAN priority field */
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/*
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* The Wiseman transmit descriptor.
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*
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* The transmit descriptor ring must be aligned to a 4K boundary,
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* and there must be an even multiple of 8 descriptors in the ring.
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*/
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typedef union wiseman_tx_fields {
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uint32_t wtxu_bits; /* bits; see below; */
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struct {
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uint8_t wtxu_status; /* Tx status */
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uint8_t wtxu_options; /* options */
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uint16_t wtxu_vlan; /* VLAN info */
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} __attribute__((__packed__)) wtxu_fields;
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} __attribute__((__packed__)) wiseman_txfields_t;
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typedef struct wiseman_txdesc {
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wiseman_addr_t wtx_addr; /* buffer address */
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uint32_t wtx_cmdlen; /* command and length */
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wiseman_txfields_t wtx_fields; /* fields; see below */
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} __attribute__((__packed__)) wiseman_txdesc_t;
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#define WTX_CMD_EOP (1U << 24) /* end of packet */
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#define WTX_CMD_IFCS (1U << 25) /* insert FCS */
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#define WTX_CMD_RS (1U << 27) /* report status */
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#define WTX_CMD_RPS (1U << 28) /* report packet sent */
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#define WTX_CMD_DEXT (1U << 29) /* descriptor extension */
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#define WTX_CMD_VLE (1U << 30) /* VLAN enable */
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#define WTX_CMD_IDE (1U << 31) /* interrupt delay enable */
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/* Descriptor types (if DEXT is set) */
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#define WTX_DTYP_C (0 << 20) /* context */
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#define WTC_DTYP_D (1U << 20) /* data */
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/* wtx_fields status bits */
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#define WTX_ST_DD (1U << 0) /* descriptor done */
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#define WTX_ST_EC (1U << 1) /* excessive collisions */
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#define WTX_ST_LC (1U << 2) /* late collision */
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#define WTX_ST_TU (1U << 3) /* transmit underrun */
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/* wtx_fields bits for IP/TCP/UDP checksum offload */
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#define WTX_IXSM (1U << 8) /* IP checksum offload */
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#define WTX_TXSM (1U << 9) /* TCP/UDP checksum offload */
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/*
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* The Livengood TCP/IP context descriptor.
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*/
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struct livengood_tcpip_ctxdesc {
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uint32_t tcpip_ipcs; /* IP checksum context */
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uint32_t tcpip_tucs; /* TCP/UDP checksum context */
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uint32_t tcpip_cmdlen;
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uint32_t tcpip_seg; /* TCP segmentation context */
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};
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/* commands for context descriptors */
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#define WTX_TCPIP_CMD_TCP (1U << 24) /* TCP context valid */
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#define WTX_TCPIP_CMD_IP (1U << 25) /* IP context valid */
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#define WTX_TCPIP_CMD_TSE (1U << 26) /* segmentation context valid */
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#define WTX_TCPIP_IPCSS(x) ((x) << 0) /* checksum start */
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#define WTX_TCPIP_IPCSO(x) ((x) << 8) /* checksum value offset */
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#define WTX_TCPIP_IPCSE(x) ((x) << 16) /* checksum end */
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#define WTX_TCPIP_TUCSS(x) ((x) << 0) /* checksum start */
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#define WTX_TCPIP_TUCSO(x) ((x) << 8) /* checksum value offset */
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#define WTX_TCPIP_TUCSE(x) ((x) << 16) /* checksum end */
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#define WTX_TCPIP_SEG_STATUS(x) ((x) << 0)
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#define WTX_TCPIP_SEG_HDRLEN(x) ((x) << 8)
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#define WTX_TCPIP_SEG_MSS(x) ((x) << 16)
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/*
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* PCI config registers used by the Wiseman.
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*/
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#define WM_PCI_MMBA PCI_MAPREG_START
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/*
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* Wiseman Control/Status Registers.
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*/
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#define WMREG_CTRL 0x0000 /* Device Control Register */
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#define CTRL_FD (1U << 0) /* full duplex */
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#define CTRL_BEM (1U << 1) /* big-endian mode */
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#define CTRL_PRIOR (1U << 2) /* 0 = receive, 1 = fair */
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#define CTRL_LRST (1U << 3) /* link reset */
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#define CTRL_ASDE (1U << 5) /* auto speed detect enable */
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#define CTRL_SLU (1U << 6) /* set link up */
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#define CTRL_ILOS (1U << 7) /* invert loss of signal */
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#define CTRL_SPEED(x) ((x) << 8) /* speed (Livengood) */
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#define CTRL_SPEED_10 CTRL_SPEED(0)
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#define CTRL_SPEED_100 CTRL_SPEED(1)
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#define CTRL_SPEED_1000 CTRL_SPEED(2)
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#define CTRL_SPEED_MASK CTRL_SPEED(3)
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#define CTRL_FRCSPD (1U << 11) /* force speed (Livengood) */
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#define CTRL_FRCFDX (1U << 12) /* force full-duplex (Livengood) */
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#define CTRL_SWDPINS_SHIFT 18
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#define CTRL_SWDPINS_MASK 0x0f
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#define CTRL_SWDPIN(x) (1U << (CTRL_SWDPINS_SHIFT + (x)))
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#define CTRL_SWDPIO_SHIFT 22
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#define CTRL_SWDPIO_MASK 0x0f
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#define CTRL_SWDPIO(x) (1U << (CTRL_SWDPIO_SHIFT + (x)))
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#define CTRL_RST (1U << 26) /* device reset */
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#define CTRL_RFCE (1U << 27) /* Rx flow control enable */
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#define CTRL_TFCE (1U << 28) /* Tx flow control enable */
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#define CTRL_VME (1U << 30) /* VLAN Mode Enable */
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#define CTRL_PHY_RESET (1U << 31) /* PHY reset (Cordova) */
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#define WMREG_STATUS 0x0008 /* Device Status Register */
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#define STATUS_FD (1U << 0) /* full duplex */
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#define STATUS_LU (1U << 1) /* link up */
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#define STATUS_TCKOK (1U << 2) /* Tx clock running */
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#define STATUS_RBCOK (1U << 3) /* Rx clock running */
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#define STATUS_TXOFF (1U << 4) /* Tx paused */
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#define STATUS_TBIMODE (1U << 5) /* fiber mode (Livengood) */
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#define STATUS_SPEED(x) ((x) << 6) /* speed indication */
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#define STATUS_SPEED_10 STATUS_SPEED(0)
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#define STATUS_SPEED_100 STATUS_SPEED(1)
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#define STATUS_SPEED_1000 STATUS_SPEED(2)
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#define STATUS_ASDV(x) ((x) << 8) /* auto speed det. val. (Livengood) */
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#define STATUS_MTXCKOK (1U << 10) /* MTXD clock running */
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#define STATUS_PCI66 (1U << 11) /* 66MHz bus (Livengood) */
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#define STATUS_BUS64 (1U << 12) /* 64-bit bus (Livengood) */
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#define STATUS_PCIX_MODE (1U << 13) /* PCIX mode (Cordova) */
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#define STATUS_PCIXSPD(x) ((x) << 14) /* PCIX speed indication (Cordova) */
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#define STATUS_PCIXSPD_50_66 STATUS_PCIXSPD(0)
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#define STATUS_PCIXSPD_66_100 STATUS_PCIXSPD(1)
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#define STATUS_PCIXSPD_100_133 STATUS_PCIXSPD(2)
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#define WMREG_EECD 0x0010 /* EEPROM Control Register */
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#define EECD_SK (1U << 0) /* clock */
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#define EECD_CS (1U << 1) /* chip select */
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#define EECD_DI (1U << 2) /* data in */
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#define EECD_DO (1U << 3) /* data out */
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#define EECD_FWE(x) ((x) << 4) /* flash write enable control */
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#define EECD_FWE_DISABLED EECD_FWE(1)
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#define EECD_FWE_ENABLED EECD_FWE(2)
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#define UWIRE_OPC_ERASE 0x04 /* MicroWire "erase" opcode */
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#define UWIRE_OPC_WRITE 0x05 /* MicroWire "write" opcode */
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#define UWIRE_OPC_READ 0x06 /* MicroWire "read" opcode */
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#define EEPROM_OFF_MACADDR 0x00 /* MAC address offset */
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#define EEPROM_OFF_CFG1 0x0a /* config word 1 */
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#define EEPROM_OFF_CFG2 0x0f /* config word 2 */
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#define EEPROM_OFF_SWDPIN 0x20 /* SWD Pins (Cordova) */
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#define EEPROM_CFG1_LVDID (1U << 0)
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#define EEPROM_CFG1_LSSID (1U << 1)
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#define EEPROM_CFG1_PME_CLOCK (1U << 2)
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#define EEPROM_CFG1_PM (1U << 3)
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#define EEPROM_CFG1_ILOS (1U << 4)
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#define EEPROM_CFG1_SWDPIO_SHIFT 5
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#define EEPROM_CFG1_SWDPIO_MASK (0xf << EEPROM_CFG1_SWDPIO_SHIFT)
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#define EEPROM_CFG1_IPS1 (1U << 8)
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#define EEPROM_CFG1_LRST (1U << 9)
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#define EEPROM_CFG1_FD (1U << 10)
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#define EEPROM_CFG1_FRCSPD (1U << 11)
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#define EEPROM_CFG1_IPS0 (1U << 12)
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#define EEPROM_CFG1_64_32_BAR (1U << 13)
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#define EEPROM_CFG2_CSR_RD_SPLIT (1U << 1)
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#define EEPROM_CFG2_APM_EN (1U << 2)
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#define EEPROM_CFG2_64_BIT (1U << 3)
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#define EEPROM_CFG2_MAX_READ (1U << 4)
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#define EEPROM_CFG2_DMCR_MAP (1U << 5)
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#define EEPROM_CFG2_133_CAP (1U << 6)
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#define EEPROM_CFG2_MSI_DIS (1U << 7)
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#define EEPROM_CFG2_FLASH_DIS (1U << 8)
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#define EEPROM_CFG2_FLASH_SIZE(x) (((x) & 3) >> 9)
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#define EEPROM_CFG2_ANE (1U << 11)
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#define EEPROM_CFG2_PAUSE(x) (((x) & 3) >> 12)
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#define EEPROM_CFG2_ASDE (1U << 14)
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#define EEPROM_CFG2_APM_PME (1U << 15)
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#define EEPROM_CFG2_SWDPIO_SHIFT 4
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#define EEPROM_CFG2_SWDPIO_MASK (0xf << EEPROM_CFG2_SWDPIO_SHIFT)
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#define EEPROM_SWDPIN_MASK 0xdf
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#define EEPROM_SWDPIN_SWDPIN_SHIFT 0
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#define EEPROM_SWDPIN_SWDPIO_SHIFT 8
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#define WMREG_CTRL_EXT 0x0018 /* Extended Device Control Register */
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#define CTRL_EXT_GPI_EN(x) (1U << (x)) /* gpin interrupt enable */
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#define CTRL_EXT_SWDPINS_SHIFT 4
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#define CTRL_EXT_SWDPINS_MASK 0x0d
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#define CTRL_EXT_SWDPIN(x) (1U << (CTRL_SWDPINS_SHIFT + (x) - 4))
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#define CTRL_EXT_SWDPIO_SHIFT 8
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#define CTRL_EXT_SWDPIO_MASK 0x0d
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#define CTRL_EXT_SWDPIO(x) (1U << (CTRL_SWDPIO_SHIFT + (x) - 4))
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#define CTRL_EXT_ASDCHK (1U << 12) /* ASD check */
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#define CTRL_EXT_EE_RST (1U << 13) /* EEPROM reset */
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#define CTRL_EXT_IPS (1U << 14) /* invert power state bit 0 */
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#define CTRL_EXT_SPD_BYPS (1U << 15) /* speed select bypass */
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#define CTRL_EXT_IPS1 (1U << 16) /* invert power state bit 1 */
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#define CTRL_EXT_RO_DIS (1U << 17) /* relaxed ordering disabled */
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#define WMREG_MDIC 0x0020 /* MDI Control Register */
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#define MDIC_DATA(x) ((x) & 0xffff)
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#define MDIC_REGADD(x) ((x) << 16)
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#define MDIC_PHYADD(x) ((x) << 21)
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#define MDIC_OP_WRITE (1U << 26)
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#define MDIC_OP_READ (2U << 26)
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#define MDIC_READY (1U << 28)
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#define MDIC_I (1U << 29) /* interrupt on MDI complete */
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#define MDIC_E (1U << 30) /* MDI error */
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#define WMREG_FCAL 0x0028 /* Flow Control Address Low */
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#define FCAL_CONST 0x00c28001 /* Flow Control MAC addr low */
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#define WMREG_FCAH 0x002c /* Flow Control Address High */
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#define FCAH_CONST 0x00000100 /* Flow Control MAC addr high */
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#define WMREG_FCT 0x0030 /* Flow Control Type */
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#define WMREG_VET 0x0038 /* VLAN Ethertype */
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#define WMREG_RAL_BASE 0x0040 /* Receive Address List */
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#define WMREG_CORDOVA_RAL_BASE 0x5400
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#define WMREG_RAL_LO(b, x) ((b) + ((x) << 3))
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#define WMREG_RAL_HI(b, x) (WMREG_RAL_LO(b, x) + 4)
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/*
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* Receive Address List: The LO part is the low-order 32-bits
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* of the MAC address. The HI part is the high-order 16-bits
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* along with a few control bits.
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*/
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#define RAL_AS(x) ((x) << 16) /* address select */
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#define RAL_AS_DEST RAL_AS(0) /* (cordova?) */
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#define RAL_AS_SOURCE RAL_AS(1) /* (cordova?) */
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#define RAL_RDR1 (1U << 30) /* put packet in alt. rx ring */
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#define RAL_AV (1U << 31) /* entry is valid */
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#define WM_RAL_TABSIZE 16
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#define WMREG_ICR 0x00c0 /* Interrupt Cause Register */
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#define ICR_TXDW (1U << 0) /* Tx desc written back */
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#define ICR_TXQE (1U << 1) /* Tx queue empty */
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#define ICR_LSC (1U << 2) /* link status change */
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#define ICR_RXSEQ (1U << 3) /* receive sequence error */
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#define ICR_RXDMT0 (1U << 4) /* Rx ring 0 nearly empty */
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#define ICR_RXO (1U << 6) /* Rx overrun */
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#define ICR_RXT0 (1U << 7) /* Rx ring 0 timer */
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#define ICR_MDAC (1U << 9) /* MDIO access complete */
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#define ICR_RXCFG (1U << 10) /* Receiving /C/ */
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#define ICR_GPI(x) (1U << (x)) /* general purpose interrupts */
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#define WMREG_ICS 0x00c8 /* Interrupt Cause Set Register */
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/* See ICR bits. */
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#define WMREG_IMS 0x00d0 /* Interrupt Mask Set Register */
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/* See ICR bits. */
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#define WMREG_IMC 0x00d8 /* Interrupt Mask Clear Register */
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/* See ICR bits. */
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#define WMREG_RCTL 0x0100 /* Receive Control */
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#define RCTL_EN (1U << 1) /* receiver enable */
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#define RCTL_SBP (1U << 2) /* store bad packets */
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#define RCTL_UPE (1U << 3) /* unicast promisc. enable */
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#define RCTL_MPE (1U << 4) /* multicast promisc. enable */
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#define RCTL_LPE (1U << 5) /* large packet enable */
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#define RCTL_LBM(x) ((x) << 6) /* loopback mode */
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#define RCTL_LBM_NONE RCTL_LBM(0)
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#define RCTL_LBM_PHY RCTL_LBM(3)
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#define RCTL_RDMTS(x) ((x) << 8) /* receive desc. min thresh size */
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#define RCTL_RDMTS_1_2 RCTL_RDMTS(0)
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#define RCTL_RDMTS_1_4 RCTL_RDMTS(1)
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#define RCTL_RDMTS_1_8 RCTL_RDMTS(2)
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#define RCTL_RDMTS_MASK RCTL_RDMTS(3)
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#define RCTL_MO(x) ((x) << 12) /* multicast offset */
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#define RCTL_BAM (1U << 15) /* broadcast accept mode */
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#define RCTL_2k (0 << 16) /* 2k Rx buffers */
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#define RCTL_1k (1 << 16) /* 1k Rx buffers */
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#define RCTL_512 (2 << 16) /* 512 byte Rx buffers */
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#define RCTL_256 (3 << 16) /* 256 byte Rx buffers */
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#define RCTL_BSEX_16k (1 << 16) /* 16k Rx buffers (BSEX) */
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#define RCTL_BSEX_8k (2 << 16) /* 8k Rx buffers (BSEX) */
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#define RCTL_BSEX_4k (3 << 16) /* 4k Rx buffers (BSEX) */
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#define RCTL_DPF (1U << 22) /* discard pause frames */
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#define RCTL_PMCF (1U << 23) /* pass MAC control frames */
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#define RCTL_BSEX (1U << 25) /* buffer size extension (Livengood) */
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#define RCTL_SECRC (1U << 26) /* strip Ethernet CRC */
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#define WMREG_OLD_RDTR0 0x0108 /* Receive Delay Timer (ring 0) */
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#define WMREG_RDTR 0x2820
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#define RDTR_FPD (1U << 31) /* flush partial descriptor */
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#define WMREG_OLD_RDBAL0 0x0110 /* Receive Descriptor Base Low (ring 0) */
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#define WMREG_RDBAL 0x2800
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#define WMREG_OLD_RDBAH0 0x0114 /* Receive Descriptor Base High (ring 0) */
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#define WMREG_RDBAH 0x2804
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#define WMREG_OLD_RDLEN0 0x0118 /* Receive Descriptor Length (ring 0) */
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#define WMREG_RDLEN 0x2808
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#define WMREG_OLD_RDH0 0x0120 /* Receive Descriptor Head (ring 0) */
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#define WMREG_RDH 0x2810
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#define WMREG_OLD_RDT0 0x0128 /* Receive Descriptor Tail (ring 0) */
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#define WMREG_RDT 0x2818
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#define WMREG_RXDCTL 0x2828 /* Receive Descriptor Control */
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#define RXDCTL_PTHRESH(x) ((x) << 0) /* prefetch threshold */
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#define RXDCTL_HTHRESH(x) ((x) << 8) /* host threshold */
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#define RXDCTL_WTHRESH(x) ((x) << 16) /* write back threshold */
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#define RXDCTL_GRAN (1U << 24) /* 0 = cacheline, 1 = descriptor */
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#define WMREG_OLD_RDTR1 0x0130 /* Receive Delay Timer (ring 1) */
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#define WMREG_OLD_RDBA1_LO 0x0138 /* Receive Descriptor Base Low (ring 1) */
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#define WMREG_OLD_RDBA1_HI 0x013c /* Receive Descriptor Base High (ring 1) */
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#define WMREG_OLD_RDLEN1 0x0140 /* Receive Drscriptor Length (ring 1) */
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#define WMREG_OLD_RDH1 0x0148
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#define WMREG_OLD_RDT1 0x0150
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#define WMREG_OLD_FCRTH 0x0160 /* Flow Control Rx Threshold Hi (OLD) */
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#define WMREG_FCRTL 0x2160 /* Flow Control Rx Threshold Lo */
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#define FCRTH_DFLT 0x00008000
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#define WMREG_OLD_FCRTL 0x0168 /* Flow Control Rx Threshold Lo (OLD) */
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#define WMREG_FCRTH 0x2168 /* Flow Control Rx Threhsold Hi */
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#define FCRTL_DFLT 0x00004000
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#define WMREG_FCTTV 0x0170 /* Flow Control Transmit Timer Value */
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#define FCTTV_DFLT 0x00000100
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#define WMREG_TXCW 0x0178 /* Transmit Configuration Word (TBI mode) */
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/* See MII ANAR_X bits. */
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#define TXCW_TxConfig (1U << 30) /* Tx Config */
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#define TXCW_ANE (1U << 31) /* Autonegotiate */
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#define WMREG_RXCW 0x0180 /* Receive Configuration Word (TBI mode) */
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/* See MII ANLPAR_X bits. */
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#define RXCW_NC (1U << 26) /* no carrier */
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#define RXCW_IV (1U << 27) /* config invalid */
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#define RXCW_CC (1U << 28) /* config change */
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#define RXCW_C (1U << 29) /* /C/ reception */
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#define RXCW_SYNCH (1U << 30) /* synchronized */
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#define RXCW_ANC (1U << 31) /* autonegotiation complete */
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#define WMREG_MTA 0x0200 /* Multicast Table Array */
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#define WMREG_CORDOVA_MTA 0x5200
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#define WMREG_TCTL 0x0400 /* Transmit Control Register */
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#define TCTL_EN (1U << 1) /* transmitter enable */
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#define TCTL_PSP (1U << 3) /* pad short packets */
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#define TCTL_CT(x) (((x) & 0xff) << 4) /* 4:11 - collision threshold */
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#define TCTL_COLD(x) (((x) & 0x3ff) << 12) /* 12:21 - collision distance */
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#define TCTL_SWXOFF (1U << 22) /* software XOFF */
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#define TCTL_RTLC (1U << 24) /* retransmit on late collision */
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#define TCTL_NRTU (1U << 25) /* no retransmit on underrun */
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#define TX_COLLISION_THRESHOLD 15
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#define TX_COLLISION_DISTANCE_HDX 64
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#define TX_COLLISION_DISTANCE_FDX 512
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#define WMREG_TQSA_LO 0x0408
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#define WMREG_TQSA_HI 0x040c
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#define WMREG_TIPG 0x0410 /* Transmit IPG Register */
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#define TIPG_IPGT(x) (x) /* IPG transmit time */
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#define TIPG_IPGR1(x) ((x) << 10) /* IPG receive time 1 */
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#define TIPG_IPGR2(x) ((x) << 20) /* IPG receive time 2 */
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#define TIPG_WM_DFLT (TIPG_IPGT(0x0a) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x0a))
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#define TIPG_LG_DFLT (TIPG_IPGT(0x06) | TIPG_IPGR1(0x08) | TIPG_IPGR2(0x06))
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#define TIPG_1000T_DFLT (TIPG_IPGT(0x08) | TIPG_IPGR1(0x08) | TIPG_IPGR2(0x06))
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#define WMREG_TQC 0x0418
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#define WMREG_OLD_TBDAL 0x0420 /* Transmit Descriptor Base Lo */
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#define WMREG_TBDAL 0x3800
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#define WMREG_OLD_TBDAH 0x0424 /* Transmit Descriptor Base Hi */
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#define WMREG_TBDAH 0x3804
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#define WMREG_OLD_TDLEN 0x0428 /* Transmit Descriptor Length */
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#define WMREG_TDLEN 0x3808
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#define WMREG_OLD_TDH 0x0430 /* Transmit Descriptor Head */
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#define WMREG_TDH 0x3810
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#define WMREG_OLD_TDT 0x0438 /* Transmit Descriptor Tail */
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#define WMREG_TDT 0x3818
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#define WMREG_OLD_TIDV 0x0440 /* Transmit Delay Interrupt Value */
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#define WMREG_TIDV 0x3820
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#define WMREG_TXDCTL 0x3828 /* Trandmit Descriptor Control */
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#define TXDCTL_PTHRESH(x) ((x) << 0) /* prefetch threshold */
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#define TXDCTL_HTHRESH(x) ((x) << 8) /* host threshold */
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#define TXDCTL_WTHRESH(x) ((x) << 16) /* write back threshold */
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#define WMREG_AIT 0x0458 /* Adaptive IFS Throttle */
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#define WMREG_VFTA 0x0600
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#define WM_MC_TABSIZE 128
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#define WM_VLAN_TABSIZE 128
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#define WMREG_PBA 0x1000 /* Packet Buffer Allocation */
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#define WMREG_TXDMAC 0x3000 /* Transfer DMA Control */
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#define TXDMAC_DPP (1U << 0) /* disable packet prefetch */
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#define WMREG_TSPMT 0x3830 /* TCP Segmentation Pad and Minimum
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Threshold (Cordova) */
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#define TSPMT_TSMT(x) (x) /* TCP seg min transfer */
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#define TSPMT_TSPBP(x) ((x) << 16) /* TCP seg pkt buf padding */
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#define WMREG_RXCSUM 0x5000 /* Receive Checksum register */
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#define RXCSUM_PCSS 0x000000ff /* Packet Checksum Start */
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#define RXCSUM_IPOFL (1U << 8) /* IP checksum offload */
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#define RXCSUM_TUOFL (1U << 9) /* TCP/UDP checksum offload */
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