627 lines
16 KiB
C
627 lines
16 KiB
C
/* $NetBSD: dma.c,v 1.20 1997/10/04 17:38:00 thorpej Exp $ */
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/*-
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* Copyright (c) 1996, 1997 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1982, 1990, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)dma.c 8.1 (Berkeley) 6/10/93
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*/
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/*
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* DMA driver
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*/
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#include <machine/hp300spu.h> /* XXX param.h includes cpu.h */
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/time.h>
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#include <sys/kernel.h>
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#include <sys/proc.h>
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#include <sys/device.h>
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#include <machine/frame.h>
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#include <machine/cpu.h>
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#include <machine/intr.h>
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#include <hp300/dev/dmareg.h>
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#include <hp300/dev/dmavar.h>
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/*
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* The largest single request will be MAXPHYS bytes which will require
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* at most MAXPHYS/NBPG+1 chain elements to describe, i.e. if none of
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* the buffer pages are physically contiguous (MAXPHYS/NBPG) and the
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* buffer is not page aligned (+1).
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*/
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#define DMAMAXIO (MAXPHYS/NBPG+1)
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struct dma_chain {
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int dc_count;
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char *dc_addr;
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};
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struct dma_channel {
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struct dmaqueue *dm_job; /* current job */
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struct dmadevice *dm_hwaddr; /* registers if DMA_C */
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struct dmaBdevice *dm_Bhwaddr; /* registers if not DMA_C */
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char dm_flags; /* misc. flags */
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u_short dm_cmd; /* DMA controller command */
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int dm_cur; /* current segment */
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int dm_last; /* last segment */
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struct dma_chain dm_chain[DMAMAXIO]; /* all segments */
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};
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struct dma_softc {
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struct dmareg *sc_dmareg; /* pointer to our hardware */
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struct dma_channel sc_chan[NDMACHAN]; /* 2 channels */
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TAILQ_HEAD(, dmaqueue) sc_queue; /* job queue */
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char sc_type; /* A, B, or C */
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int sc_ipl; /* our interrupt level */
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void *sc_ih; /* interrupt cookie */
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} dma_softc;
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/* types */
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#define DMA_B 0
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#define DMA_C 1
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/* flags */
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#define DMAF_PCFLUSH 0x01
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#define DMAF_VCFLUSH 0x02
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#define DMAF_NOINTR 0x04
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int dmaintr __P((void *));
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#ifdef DEBUG
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int dmadebug = 0;
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#define DDB_WORD 0x01 /* same as DMAGO_WORD */
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#define DDB_LWORD 0x02 /* same as DMAGO_LWORD */
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#define DDB_FOLLOW 0x04
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#define DDB_IO 0x08
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void dmatimeout __P((void *));
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int dmatimo[NDMACHAN];
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long dmahits[NDMACHAN];
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long dmamisses[NDMACHAN];
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long dmabyte[NDMACHAN];
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long dmaword[NDMACHAN];
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long dmalword[NDMACHAN];
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#endif
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/*
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* Initialize the DMA engine, called by dioattach()
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*/
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void
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dmainit()
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{
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struct dma_softc *sc = &dma_softc;
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struct dmareg *dma;
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struct dma_channel *dc;
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int i;
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char rev;
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/* There's just one. */
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sc->sc_dmareg = (struct dmareg *)DMA_BASE;
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dma = sc->sc_dmareg;
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/*
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* Determine the DMA type. A DMA_A or DMA_B will fail the
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* following probe.
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*
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* XXX Don't know how to easily differentiate the A and B cards,
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* so we just hope nobody has an A card (A cards will work if
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* splbio works out to ipl 3).
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*/
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if (badbaddr((char *)&dma->dma_id[2])) {
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rev = 'B';
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#if !defined(HP320)
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panic("dmainit: DMA card requires hp320 support");
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#endif
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} else
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rev = dma->dma_id[2];
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sc->sc_type = (rev == 'B') ? DMA_B : DMA_C;
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TAILQ_INIT(&sc->sc_queue);
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for (i = 0; i < NDMACHAN; i++) {
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dc = &sc->sc_chan[i];
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dc->dm_job = NULL;
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switch (i) {
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case 0:
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dc->dm_hwaddr = &dma->dma_chan0;
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dc->dm_Bhwaddr = &dma->dma_Bchan0;
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break;
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case 1:
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dc->dm_hwaddr = &dma->dma_chan1;
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dc->dm_Bhwaddr = &dma->dma_Bchan1;
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break;
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default:
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panic("dmainit: more than 2 channels?");
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/* NOTREACHED */
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}
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}
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#ifdef DEBUG
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/* make sure timeout is really not needed */
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timeout(dmatimeout, sc, 30 * hz);
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#endif
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printf("98620%c, 2 channels, %d bit DMA\n",
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rev, (rev == 'B') ? 16 : 32);
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/*
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* Defer hooking up our interrupt until the first
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* DMA-using controller has hooked up theirs.
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*/
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sc->sc_ih = NULL;
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}
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/*
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* Compute the ipl and (re)establish the interrupt handler
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* for the DMA controller.
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*/
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void
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dmacomputeipl()
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{
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struct dma_softc *sc = &dma_softc;
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if (sc->sc_ih != NULL)
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intr_disestablish(sc->sc_ih);
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/*
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* Our interrupt level must be as high as the highest
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* device using DMA (i.e. splbio).
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*/
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sc->sc_ipl = PSLTOIPL(hp300_bioipl);
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sc->sc_ih = intr_establish(dmaintr, sc, sc->sc_ipl, IPL_BIO);
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}
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int
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dmareq(dq)
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struct dmaqueue *dq;
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{
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struct dma_softc *sc = &dma_softc;
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int i, chan, s;
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#if 1
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s = splhigh(); /* XXXthorpej */
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#else
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s = splbio();
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#endif
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chan = dq->dq_chan;
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for (i = NDMACHAN - 1; i >= 0; i--) {
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/*
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* Can we use this channel?
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*/
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if ((chan & (1 << i)) == 0)
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continue;
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/*
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* We can use it; is it busy?
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*/
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if (sc->sc_chan[i].dm_job != NULL)
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continue;
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/*
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* Not busy; give the caller this channel.
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*/
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sc->sc_chan[i].dm_job = dq;
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dq->dq_chan = i;
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splx(s);
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return (1);
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}
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/*
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* Couldn't get a channel now; put this in the queue.
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*/
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TAILQ_INSERT_TAIL(&sc->sc_queue, dq, dq_list);
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splx(s);
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return (0);
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}
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void
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dmafree(dq)
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struct dmaqueue *dq;
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{
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int unit = dq->dq_chan;
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struct dma_softc *sc = &dma_softc;
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struct dma_channel *dc = &sc->sc_chan[unit];
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struct dmaqueue *dn;
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int chan, s;
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#if 1
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s = splhigh(); /* XXXthorpej */
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#else
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s = splbio();
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#endif
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#ifdef DEBUG
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dmatimo[unit] = 0;
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#endif
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DMA_CLEAR(dc);
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#if defined(CACHE_HAVE_PAC) || defined(M68040)
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/*
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* XXX we may not always go thru the flush code in dmastop()
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*/
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if (dc->dm_flags & DMAF_PCFLUSH) {
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PCIA();
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dc->dm_flags &= ~DMAF_PCFLUSH;
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}
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#endif
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#if defined(CACHE_HAVE_VAC)
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if (dc->dm_flags & DMAF_VCFLUSH) {
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/*
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* 320/350s have VACs that may also need flushing.
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* In our case we only flush the supervisor side
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* because we know that if we are DMAing to user
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* space, the physical pages will also be mapped
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* in kernel space (via vmapbuf) and hence cache-
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* inhibited by the pmap module due to the multiple
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* mapping.
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*/
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DCIS();
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dc->dm_flags &= ~DMAF_VCFLUSH;
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}
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#endif
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/*
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* Channel is now free. Look for another job to run on this
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* channel.
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*/
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dc->dm_job = NULL;
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chan = 1 << unit;
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for (dn = sc->sc_queue.tqh_first; dn != NULL;
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dn = dn->dq_list.tqe_next) {
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if (dn->dq_chan & chan) {
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/* Found one... */
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TAILQ_REMOVE(&sc->sc_queue, dn, dq_list);
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dc->dm_job = dn;
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dn->dq_chan = dq->dq_chan;
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splx(s);
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/* Start the initiator. */
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(*dn->dq_start)(dn->dq_softc);
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return;
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}
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}
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splx(s);
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}
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void
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dmago(unit, addr, count, flags)
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int unit;
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char *addr;
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int count;
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int flags;
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{
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struct dma_softc *sc = &dma_softc;
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struct dma_channel *dc = &sc->sc_chan[unit];
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char *dmaend = NULL;
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int seg, tcount;
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if (count > MAXPHYS)
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panic("dmago: count > MAXPHYS");
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#if defined(HP320)
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if (sc->sc_type == DMA_B && (flags & DMAGO_LWORD))
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panic("dmago: no can do 32-bit DMA");
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#endif
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#ifdef DEBUG
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if (dmadebug & DDB_FOLLOW)
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printf("dmago(%d, %p, %x, %x)\n",
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unit, addr, count, flags);
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if (flags & DMAGO_LWORD)
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dmalword[unit]++;
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else if (flags & DMAGO_WORD)
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dmaword[unit]++;
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else
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dmabyte[unit]++;
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#endif
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/*
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* Build the DMA chain
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*/
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for (seg = 0; count > 0; seg++) {
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dc->dm_chain[seg].dc_addr = (char *) kvtop(addr);
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#if defined(M68040)
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/*
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* Push back dirty cache lines
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*/
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if (mmutype == MMU_68040)
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DCFP((vm_offset_t)dc->dm_chain[seg].dc_addr);
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#endif
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if (count < (tcount = NBPG - ((int)addr & PGOFSET)))
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tcount = count;
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dc->dm_chain[seg].dc_count = tcount;
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addr += tcount;
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count -= tcount;
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if (flags & DMAGO_LWORD)
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tcount >>= 2;
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else if (flags & DMAGO_WORD)
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tcount >>= 1;
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/*
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* Try to compact the DMA transfer if the pages are adjacent.
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* Note: this will never happen on the first iteration.
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*/
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if (dc->dm_chain[seg].dc_addr == dmaend
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#if defined(HP320)
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/* only 16-bit count on 98620B */
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&& (sc->sc_type != DMA_B ||
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dc->dm_chain[seg - 1].dc_count + tcount <= 65536)
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#endif
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) {
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#ifdef DEBUG
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dmahits[unit]++;
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#endif
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dmaend += dc->dm_chain[seg].dc_count;
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dc->dm_chain[--seg].dc_count += tcount;
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} else {
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#ifdef DEBUG
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dmamisses[unit]++;
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#endif
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dmaend = dc->dm_chain[seg].dc_addr +
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dc->dm_chain[seg].dc_count;
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dc->dm_chain[seg].dc_count = tcount;
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}
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}
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dc->dm_cur = 0;
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dc->dm_last = --seg;
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dc->dm_flags = 0;
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/*
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* Set up the command word based on flags
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*/
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dc->dm_cmd = DMA_ENAB | DMA_IPL(sc->sc_ipl) | DMA_START;
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if ((flags & DMAGO_READ) == 0)
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dc->dm_cmd |= DMA_WRT;
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if (flags & DMAGO_LWORD)
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dc->dm_cmd |= DMA_LWORD;
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else if (flags & DMAGO_WORD)
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dc->dm_cmd |= DMA_WORD;
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if (flags & DMAGO_PRI)
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dc->dm_cmd |= DMA_PRI;
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#if defined(M68040)
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/*
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* On the 68040 we need to flush (push) the data cache before a
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* DMA (already done above) and flush again after DMA completes.
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* In theory we should only need to flush prior to a write DMA
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* and purge after a read DMA but if the entire page is not
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* involved in the DMA we might purge some valid data.
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*/
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if (mmutype == MMU_68040 && (flags & DMAGO_READ))
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dc->dm_flags |= DMAF_PCFLUSH;
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#endif
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#if defined(CACHE_HAVE_PAC)
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/*
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* Remember if we need to flush external physical cache when
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* DMA is done. We only do this if we are reading (writing memory).
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*/
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if (ectype == EC_PHYS && (flags & DMAGO_READ))
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dc->dm_flags |= DMAF_PCFLUSH;
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#endif
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#if defined(CACHE_HAVE_VAC)
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if (ectype == EC_VIRT && (flags & DMAGO_READ))
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dc->dm_flags |= DMAF_VCFLUSH;
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#endif
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/*
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* Remember if we can skip the dma completion interrupt on
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* the last segment in the chain.
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*/
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if (flags & DMAGO_NOINT) {
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if (dc->dm_cur == dc->dm_last)
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dc->dm_cmd &= ~DMA_ENAB;
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else
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dc->dm_flags |= DMAF_NOINTR;
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}
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#ifdef DEBUG
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if (dmadebug & DDB_IO) {
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if (((dmadebug&DDB_WORD) && (dc->dm_cmd&DMA_WORD)) ||
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((dmadebug&DDB_LWORD) && (dc->dm_cmd&DMA_LWORD))) {
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printf("dmago: cmd %x, flags %x\n",
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dc->dm_cmd, dc->dm_flags);
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for (seg = 0; seg <= dc->dm_last; seg++)
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printf(" %d: %d@%p\n", seg,
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dc->dm_chain[seg].dc_count,
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dc->dm_chain[seg].dc_addr);
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}
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}
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dmatimo[unit] = 1;
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#endif
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DMA_ARM(sc, dc);
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}
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void
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dmastop(unit)
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int unit;
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{
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struct dma_softc *sc = &dma_softc;
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struct dma_channel *dc = &sc->sc_chan[unit];
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#ifdef DEBUG
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if (dmadebug & DDB_FOLLOW)
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printf("dmastop(%d)\n", unit);
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dmatimo[unit] = 0;
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#endif
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DMA_CLEAR(dc);
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#if defined(CACHE_HAVE_PAC) || defined(M68040)
|
|
if (dc->dm_flags & DMAF_PCFLUSH) {
|
|
PCIA();
|
|
dc->dm_flags &= ~DMAF_PCFLUSH;
|
|
}
|
|
#endif
|
|
|
|
#if defined(CACHE_HAVE_VAC)
|
|
if (dc->dm_flags & DMAF_VCFLUSH) {
|
|
/*
|
|
* 320/350s have VACs that may also need flushing.
|
|
* In our case we only flush the supervisor side
|
|
* because we know that if we are DMAing to user
|
|
* space, the physical pages will also be mapped
|
|
* in kernel space (via vmapbuf) and hence cache-
|
|
* inhibited by the pmap module due to the multiple
|
|
* mapping.
|
|
*/
|
|
DCIS();
|
|
dc->dm_flags &= ~DMAF_VCFLUSH;
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* We may get this interrupt after a device service routine
|
|
* has freed the dma channel. So, ignore the intr if there's
|
|
* nothing on the queue.
|
|
*/
|
|
if (dc->dm_job != NULL)
|
|
(*dc->dm_job->dq_done)(dc->dm_job->dq_softc);
|
|
}
|
|
|
|
int
|
|
dmaintr(arg)
|
|
void *arg;
|
|
{
|
|
struct dma_softc *sc = arg;
|
|
struct dma_channel *dc;
|
|
int i, stat;
|
|
int found = 0;
|
|
|
|
#ifdef DEBUG
|
|
if (dmadebug & DDB_FOLLOW)
|
|
printf("dmaintr\n");
|
|
#endif
|
|
for (i = 0; i < NDMACHAN; i++) {
|
|
dc = &sc->sc_chan[i];
|
|
stat = DMA_STAT(dc);
|
|
if ((stat & DMA_INTR) == 0)
|
|
continue;
|
|
found++;
|
|
#ifdef DEBUG
|
|
if (dmadebug & DDB_IO) {
|
|
if (((dmadebug&DDB_WORD) && (dc->dm_cmd&DMA_WORD)) ||
|
|
((dmadebug&DDB_LWORD) && (dc->dm_cmd&DMA_LWORD)))
|
|
printf("dmaintr: flags %x unit %d stat %x next %d\n",
|
|
dc->dm_flags, i, stat, dc->dm_cur + 1);
|
|
}
|
|
if (stat & DMA_ARMED)
|
|
printf("dma channel %d: intr when armed\n", i);
|
|
#endif
|
|
/*
|
|
* Load the next segemnt, or finish up if we're done.
|
|
*/
|
|
dc->dm_cur++;
|
|
if (dc->dm_cur <= dc->dm_last) {
|
|
#ifdef DEBUG
|
|
dmatimo[i] = 1;
|
|
#endif
|
|
/*
|
|
* If we're the last segment, disable the
|
|
* completion interrupt, if necessary.
|
|
*/
|
|
if (dc->dm_cur == dc->dm_last &&
|
|
(dc->dm_flags & DMAF_NOINTR))
|
|
dc->dm_cmd &= ~DMA_ENAB;
|
|
DMA_CLEAR(dc);
|
|
DMA_ARM(sc, dc);
|
|
} else
|
|
dmastop(i);
|
|
}
|
|
return(found);
|
|
}
|
|
|
|
#ifdef DEBUG
|
|
void
|
|
dmatimeout(arg)
|
|
void *arg;
|
|
{
|
|
int i, s;
|
|
struct dma_softc *sc = arg;
|
|
|
|
for (i = 0; i < NDMACHAN; i++) {
|
|
s = splbio();
|
|
if (dmatimo[i]) {
|
|
if (dmatimo[i] > 1)
|
|
printf("dma channel %d timeout #%d\n",
|
|
i, dmatimo[i]-1);
|
|
dmatimo[i]++;
|
|
}
|
|
splx(s);
|
|
}
|
|
timeout(dmatimeout, sc, 30 * hz);
|
|
}
|
|
#endif
|