132 lines
4.6 KiB
C
132 lines
4.6 KiB
C
/* $NetBSD: locore.h,v 1.4 1997/05/25 23:00:40 jonathan Exp $ */
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/*
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* Copyright 1996 The Board of Trustees of The Leland Stanford
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* Junior University. All Rights Reserved.
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*
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* Permission to use, copy, modify, and distribute this
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* software and its documentation for any purpose and without
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* fee is hereby granted, provided that the above copyright
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* notice appear in all copies. Stanford University
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* makes no representations about the suitability of this
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* software for any purpose. It is provided "as is" without
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* express or implied warranty.
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*/
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/*
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* Jump table for MIPS cpu locore functions that are implemented
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* differently on different generations, or instruction-level
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* archtecture (ISA) level, the Mips family.
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* The following functions must be provided for each mips ISA level:
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*
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*
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* MachConfigCache
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* MachFlushCache
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* MachFlushDCache
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* MachFlushICache
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* MachForceCacheUpdate
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* MachSetPID
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* MachTLBFlush
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* MachTLBFlushAddr __P()
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* MachTLBUpdate (u_int, (pt_entry_t?) u_int);
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* MachTLBWriteIndexed
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*
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* We currently provide support for:
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*
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* r2000 and r3000 (mips ISA-I)
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* r4000 and r4400 in 32-bit mode (mips ISA-III?)
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*/
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#ifndef _MIPS_LOCORE_H
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#define _MIPS_LOCORE_H
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/*
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* locore functions used by vm_machdep.c.
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* These are not yet CPU-model specific.
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*/
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struct user;
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extern int copykstack __P((struct user *up));
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extern void MachSaveCurFPState __P((struct proc *p));
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extern int switch_exit __P((void)); /* XXX never really returns? */
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extern void blkclr __P((caddr_t val, int size)); /* bulk aligned bzero */
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/* MIPS-generic locore functions used by trap.c */
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extern void MachFPTrap __P((u_int statusReg, u_int CauseReg, u_int pc));
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/*
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* locore service routine for exeception vectors. Used outside locore
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* only to print them by name in stack tracebacks
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*/
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extern void mips1_KernIntr __P((void));
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extern void mips1_ConfigCache __P((void));
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extern void mips1_FlushCache __P((void));
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extern void mips1_FlushDCache __P((vm_offset_t addr, vm_offset_t len));
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extern void mips1_FlushICache __P((vm_offset_t addr, vm_offset_t len));
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extern void mips1_ForceCacheUpdate __P((void));
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extern void mips1_SetPID __P((int pid));
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extern void mips1_TLBFlush __P((void));
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extern void mips1_TLBFlushAddr __P( /* XXX Really pte highpart ? */
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(vm_offset_t addr));
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extern void mips1_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int));
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extern void mips1_TLBWriteIndexed __P((u_int index, u_int high,
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u_int low));
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extern void mips3_KernIntr __P((void));
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extern void mips3_ConfigCache __P((void));
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extern void mips3_FlushCache __P((void));
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extern void mips3_FlushDCache __P((vm_offset_t addr, vm_offset_t len));
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extern void mips3_FlushICache __P((vm_offset_t addr, vm_offset_t len));
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extern void mips3_ForceCacheUpdate __P((void));
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extern void mips3_SetPID __P((int pid));
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extern void mips3_TLBFlush __P((void));
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extern void mips3_TLBFlushAddr __P( /* XXX Really pte highpart ? */
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(vm_offset_t addr));
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extern void mips3_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int));
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extern void mips3_TLBWriteIndexed __P((u_int index, u_int high,
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u_int low));
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/*
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* A vector with an entry for each mips-ISA-level dependent
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* locore function, and macros which jump through it.
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* XXX the macro names are chosen to be compatible with the old
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* Sprite coding-convention names used in 4.4bsd/pmax.
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*/
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typedef struct {
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void (*configCache) __P((void));
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void (*flushCache) __P((void));
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void (*flushDCache) __P((vm_offset_t addr, vm_offset_t len));
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void (*flushICache) __P((vm_offset_t addr, vm_offset_t len));
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void (*forceCacheUpdate) __P((void));
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void (*setTLBpid) __P((int pid));
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void (*tlbFlush) __P((void));
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void (*tlbFlushAddr) __P((vm_offset_t)); /* XXX Really pte highpart ? */
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void (*tlbUpdate) __P((u_int highreg, u_int lowreg));
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void (*tlbWriteIndexed) __P((u_int, u_int, u_int));
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} mips_locore_jumpvec_t;
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/*
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* The "active" locore-fuction vector, and
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*/
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extern mips_locore_jumpvec_t mips_locore_jumpvec;
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extern mips_locore_jumpvec_t r2000_locore_vec;
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extern mips_locore_jumpvec_t r4000_locore_vec;
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#define MachConfigCache (*(mips_locore_jumpvec.configCache))
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#define MachFlushCache (*(mips_locore_jumpvec.flushCache))
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#define MachFlushDCache (*(mips_locore_jumpvec.flushDCache))
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#define MachFlushICache (*(mips_locore_jumpvec.flushICache))
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#define MachForceCacheUpdate (*(mips_locore_jumpvec.forceCacheUpdate))
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#define MachSetPID (*(mips_locore_jumpvec.setTLBpid))
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#define MachTLBFlush (*(mips_locore_jumpvec.tlbFlush))
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#define MachTLBFlushAddr (*(mips_locore_jumpvec.tlbFlushAddr))
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#define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate))
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#define MachTLBWriteIndexed (*(mips_locore_jumpvec.tlbWriteIndexed))
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#endif /* _MIPS_LOCORE_H */
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