97 lines
3.8 KiB
C
97 lines
3.8 KiB
C
/* $NetBSD: irongatereg.h,v 1.2 2000/06/26 02:42:10 thorpej Exp $ */
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/*-
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* Copyright (c) 2000 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Register definitions for the AMD 751 (``Irongate'') core logic
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* chipset.
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*/
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/*
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* Address map.
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*
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* This from the Tsunami address map:
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* EV6 has a new superpage which can pass through 44 address bits. (Umm, a
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* superduperpage?) But, the firmware doesn't turn it on, so we use the old
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* one and let the HW sign extend va/pa<40> to get us the pa<43> that makes
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* the needed I/O space access. This is just as well; it means we don't have
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* to worry about which GENERIC code might get called on other CPU models.
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*
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* E.g., we want this: 0x0801##fc00##0000
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* We use this: 0x0101##fc00##0000
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* ...mix in the old SP: 0xffff##fc00##0000##0000
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* ...after PA sign ext: 0xffff##ff01##fc00##0000
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* (PA<42:41> ignored)
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*
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* PCI memory and RAM: 0000.0000.0000
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* IACK 0001.f800.0000
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* PCI I/O: 0001.fc00.0000
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* AMD 751 (also in PCI config space): 0001.fe00.0000
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*/
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/*
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* This hack allows us to map the I/O address space without using
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* the KSEG sign extension hack.
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*/
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#define IRONGATE_PHYSADDR(x) \
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(((x) & ~0x0100##0000##0000) | 0x0800##0000##0000)
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#define IRONGATE_KSEG_BIAS 0x0100##0000##0000UL
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#define IRONGATE_MEM_BASE (IRONGATE_KSEG_BIAS | 0x0000##0000##0000UL)
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#define IRONGATE_IACK_BASE (IRONGATE_KSEG_BIAS | 0x0001##f800##0000UL)
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#define IRONGATE_IO_BASE (IRONGATE_KSEG_BIAS | 0x0001##fc00##0000UL)
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#define IRONGATE_SELF_BASE (IRONGATE_KSEG_BIAS | 0x0001##fe00##0000UL)
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/*
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* PCI configuration register access using done by using
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* ``configuration mode 1'' (in PC lingo), using the I/O
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* space addresses described in the PCI Local Bus Specification
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* Revision 2.2.
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*/
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#define IRONGATE_CONFADDR 0x0cf8
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#define IRONGATE_CONFDATA 0x0cfc
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#define CONFADDR_ENABLE 0x80000000U
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/*
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* The AMD 751 PCI-Host bridge is located at device 0, and the
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* AGP controller (seen as a PCI-PCI bridge) is at device 1.
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*/
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#define IRONGATE_PCIHOST_DEV 0
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#define IRONGATE_PCIAGP_DEV 1
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