161 lines
5.0 KiB
C
161 lines
5.0 KiB
C
/* $NetBSD: pte.h,v 1.5 2003/11/21 22:57:14 matt Exp $ */
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/*-
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* Copyright (C) 2003 Matt Thomas
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* Copyright (C) 1995, 1996 Wolfgang Solfrank.
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* Copyright (C) 1995, 1996 TooLs GmbH.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by TooLs GmbH.
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* 4. The name of TooLs GmbH may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _POWERPC_OEA_PTE_H_
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#define _POWERPC_OEA_PTE_H_
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#include <sys/queue.h>
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/*
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* Page Table Entries
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*/
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#ifndef _LOCORE
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struct pte {
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register_t pte_hi;
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register_t pte_lo;
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};
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struct pteg {
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struct pte pt[8];
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};
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#endif /* _LOCORE */
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/* High word: */
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#ifdef PPC_OEA64
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#define PTE_VALID 0x00000001
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#define PTE_HID 0x00000002
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#define PTE_API 0x00000f80
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#define PTE_API_SHFT 7
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#define PTE_VSID_SHFT 12
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#define PTE_VSID (~0xfffL)
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#else
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#define PTE_VALID 0x80000000
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#define PTE_VSID 0x7fffff80
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#define PTE_VSID_SHFT 7
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#define PTE_VSID_LEN 24
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#define PTE_HID 0x00000040
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#define PTE_API 0x0000003f
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#define PTE_API_SHFT 0
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#endif /* PPC_OEA64 */
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/* Low word: */
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#define PTE_RPGN (~0xfffL)
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#define PTE_RPGN_SHFT 12
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#define PTE_REF 0x00000100
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#define PTE_CHG 0x00000080
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#define PTE_W 0x00000040 /* 1 = write-through, 0 = write-back */
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#define PTE_I 0x00000020 /* cache inhibit */
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#define PTE_M 0x00000010 /* memory coherency enable */
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#define PTE_G 0x00000008 /* guarded region (not on 601) */
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#define PTE_WIMG (PTE_W|PTE_I|PTE_M|PTE_G)
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#define PTE_IG (PTE_I|PTE_G)
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#define PTE_PP 0x00000003
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#define PTE_SO 0x00000000 /* Super. Only (U: XX, S: RW) */
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#define PTE_SW 0x00000001 /* Super. Write-Only (U: RO, S: RW) */
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#define PTE_BW 0x00000002 /* Supervisor (U: RW, S: RW) */
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#define PTE_BR 0x00000003 /* Both Read Only (U: RO, S: RO) */
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#define PTE_RW PTE_BW
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#define PTE_RO PTE_BR
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#define PTE_EXEC 0x00000200 /* pseudo bit; page is exec */
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/*
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* Extract bits from address
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*/
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#define ADDR_SR (~0x0fffffffL)
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#define ADDR_SR_SHFT 28
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#define ADDR_PIDX 0x0ffff000
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#define ADDR_PIDX_SHFT 12
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#ifdef PPC_OEA64
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#define ADDR_API_SHFT 23 /* API is 5 bits */
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#else
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#define ADDR_API_SHFT 22 /* API is 6 bits */
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#endif /* PPC_OEA64 */
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#define ADDR_POFF 0x00000fff
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#ifdef PPC_OEA64
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/*
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* Segment Table Element
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*/
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#ifndef _LOCORE
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struct ste {
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register_t ste_hi;
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register_t ste_lo;
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};
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struct steg {
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struct ste st[8];
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};
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#endif /* _LOCORE */
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/* High Word */
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#define STE_VALID 0x00000080
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#define STE_TYPE 0x00000040
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#define STE_SUKEY 0x00000020 /* Super-state protection */
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#define STE_PRKEY 0x00000010 /* User-state protection */
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#define STE_NOEXEC 0x00000008 /* No-execute protection bit */
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#define STE_ESID (~0x0fffffffL) /* Effective Segment ID */
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#define STE_ESID_SHFT 28
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#define STE_ESID_MASK 0x0000001f /* low 5 bits of the ESID */
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/* Low Word */
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#define STE_VSID (~0xfffL) /* Virtual Segment ID */
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#define STE_VSID_SHFT 12
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#defien STE_VSID_WIDTH 52
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#define SR_VSID_SHFT STE_VSID_SHFT /* compatibility with PPC_OEA */
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#define SR_VSID_WIDTH STE_VSID_WIDTH /* compatibility with PPC_OEA */
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#define SR_KEY_LEN 9 /* 64 groups of 8 segment entries */
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#else /* !defined(PPC_OEA64) */
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/*
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* Segment registers
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*/
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#define SR_KEY_LEN 4 /* 16 segment registers */
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#define SR_TYPE 0x80000000 /* T=0 selects memory format */
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#define SR_SUKEY 0x40000000 /* Supervisor protection key */
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#define SR_PRKEY 0x20000000 /* User protection key */
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#define SR_NOEXEC 0x10000000 /* No-execute protection bit */
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#define SR_VSID_SHFT 0 /* Starts at LSB */
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#define SR_VSID_WIDTH 24 /* Goes for 24 bits */
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#endif /* PPC_OEA64 */
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/* Virtual segment ID */
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#define SR_VSID (((1L << SR_VSID_WIDTH) - 1) << SR_VSID_SHFT)
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#endif /* _POWERPC_OEA_PTE_H_ */
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