08bde987bb
in preparation for future mvmeppc and mvme88k ports. This needs a bit if tidying up to make it trully shareable, which will happen as the new mvme ports are added.
317 lines
14 KiB
C
317 lines
14 KiB
C
/* $NetBSD: pcctworeg.h,v 1.1 2002/02/12 20:38:49 scw Exp $ */
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/*-
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* Copyright (c) 1999, 2002 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Steve C. Woodford
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Register definitions for the PCCchip2 device, and offset to the
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* various subordinate devices which hang off it.
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*/
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#ifndef _MVME_PCCTWOREG_H
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#define _MVME_PCCTWOREG_H
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/*
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* Offsets to the various devices which hang off the PCCChip2.
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* Note that these are offsets from the base of the PCCChip2's
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* own registers.
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*/
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#define PCCTWO_REG_OFF 0x00000 /* Offset of PCCChip2's own registers */
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#define PCCTWO_LPT_OFF 0x00000 /* Offset of parallel port registers */
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#define PCCTWO_SCC_OFF 0x03000 /* Offset of CD2401 Serial Comms chip */
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#define PCCTWO_IE_OFF 0x04000 /* Offset of 82596 LAN controller */
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#define PCCTWO_NCRSC_OFF 0x05000 /* Offset of NCR53C710 SCSI chip */
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/*
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* The two devices on mvme1[67]2's MCchip
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*/
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#define MCCHIP_ZS0_OFF 0x03000
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#define MCCHIP_ZS1_OFF 0x03800
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/*
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* This is needed to figure out the boot device.
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* (The physical address of the boot device's registers are passed in
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* from the Boot ROM)
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*/
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#define PCCTWO_PADDR(off) ((void *)(0xfff42000u + (off)))
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/*
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* The layout of the PCCchip2's Registers.
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* Each one is 8-bits wide, unless otherwise indicated.
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*/
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#define PCC2REG_CHIP_ID 0x00 /* Chip ID */
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#define PCC2REG_CHIP_REVISION 0x01 /* Chip Revision */
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#define PCC2REG_GENERAL_CONTROL 0x02 /* General Control */
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#define PCC2REG_VECTOR_BASE 0x03 /* Vector Base */
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#define PCC2REG_TIMER1_COMPARE 0x04 /* Tick Timer 1 Compare (32-bit) */
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#define PCC2REG_TIMER1_COUNTER 0x08 /* Tick Timer 1 Counter (32-bit) */
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#define PCC2REG_TIMER2_COMPARE 0x0c /* Tick Timer 2 Compare (32-bit) */
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#define PCC2REG_TIMER2_COUNTER 0x10 /* Tick Timer 2 Counter (32-bit) */
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#define PCC2REG_PRESCALE_COUNT 0x14 /* Prescaler Count */
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#define PCC2REG_PRESCALE_ADJUST 0x15 /* Prescaler Clock Adjust */
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#define PCC2REG_TIMER2_CONTROL 0x16 /* Tick Timer 2 Control */
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#define PCC2REG_TIMER1_CONTROL 0x17 /* Tick Timer 1 Control */
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#define PCC2REG_GPIO_ICSR 0x18 /* GP Input Interrupt Control */
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#define PCC2REG_GPIO_CONTROL 0x19 /* GP Input/Output Control */
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#define PCC2REG_TIMER2_ICSR 0x1a /* Tick Timer 2 Interrupt Control */
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#define PCC2REG_TIMER1_ICSR 0x1b /* Tick Timer 1 Interrupt Control */
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#define PCC2REG_SCC_ERR_STATUS 0x1c /* SCC Error Status */
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#define PCC2REG_SCC_MODEM_ICSR 0x1d /* SCC Modem Interrupt Control */
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#define PCC2REG_SCC_TX_ICSR 0x1e /* SCC Transmit Interrupt Control */
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#define PCC2REG_SCC_RX_ICSR 0x1f /* SCC Receive Interrupt Control */
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#define PCC2REG_SCC_MODEM_PIACK 0x23 /* SCC Modem PIACK */
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#define PCC2REG_SCC_TX_PIACK 0x25 /* SCC Transmit PIACK */
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#define PCC2REG_SCC_RX_PIACK 0x27 /* SCC Receive PIACK */
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#define PCC2REG_ETH_ERR_STATUS 0x28 /* LANC Error Status */
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#define PCC2REG_ETH_ICSR 0x2a /* LANC Interrupt Control */
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#define PCC2REG_ETH_BERR_STATUS 0x2b /* LANC Bus Error Interrupt Ctrl */
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#define PCC2REG_SCSI_ERR_STATUS 0x2c /* SCSI Error Status */
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#define PCC2REG_SCSI_ICSR 0x2f /* SCSI Interrupt Control */
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#define PCC2REG_PRT_ACK_ICSR 0x30 /* Printer ACK Interrupt Control */
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#define PCC2REG_PRT_FAULT_ICSR 0x31 /* Printer FAULT Interrupt Ctrl */
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#define PCC2REG_PRT_SEL_ICSR 0x32 /* Printer SEL Interrupt Control */
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#define PCC2REG_PRT_PE_ICSR 0x33 /* Printer PE Interrupt Control */
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#define PCC2REG_PRT_BUSY_ICSR 0x34 /* Printer BUSY Interrupt Control */
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#define PCC2REG_PRT_INPUT_STATUS 0x36 /* Printer Input Status */
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#define PCC2REG_PRT_CONTROL 0x37 /* Printer Port Control */
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#define PCC2REG_CHIP_SPEED 0x38 /* Chip Speed (16-bit) */
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#define PCC2REG_PRT_DATA 0x3a /* Printer Data (16-bit) */
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#define PCC2REG_IRQ_LEVEL 0x3e /* Interrupt Priority Level */
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#define PCC2REG_IRQ_MASK 0x3f /* Interrupt Mask */
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/*
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* Additions to the registers for the MCChip. Some of these overlap with
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* the PCCchip2's registers, but only where hardware is not present, eg.
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* the printer registers.
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*/
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#define MCCHIPREG_TIMER4_ICSR 0x18 /* Tick timer 4 interrupt control */
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#define MCCHIPREG_TIMER3_ICSR 0x19 /* Tick timer 4 interrupt control */
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#define MCCHIPREG_PARERR_ICSR 0x1c /* Parity error interrupt control */
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#define MCCHIPREG_SCC_ICSR 0x1d /* ZS-85230 interrupt control */
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#define MCCHIPREG_TIMER4_CTRL 0x1e /* Tick timer 4 control */
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#define MCCHIPREG_TIMER3_CTRL 0x1f /* Tick timer 3 control */
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#define MCCHIPREG_DRAM_BAR 0x20 /* DRAM Base Address (16-bits) */
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#define MCCHIPREG_SRAM_BAR 0x22 /* SRAM Base Address (16-bits) */
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#define MCCHIPREG_DRAM_SIZE 0x24 /* DRAM Size */
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#define MCCHIPREG_RAM_OPTIONS 0x25 /* DRAM/SRAM Options */
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#define MCCHIPREG_SRAM_SIZE 0x26 /* SRAM Size */
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#define MCCHIPREG_GP_INPUTS 0x2d /* General Purpose Inputs */
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#define MCCHIPREG_162_VERSION 0x2e /* MVME162-LX Series Version */
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#define MCCHIPREG_TIMER3_COMP 0x30 /* Tick Timer 3 Compare (32-bit) */
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#define MCCHIPREG_TIMER3_CNTR 0x34 /* Tick Timer 3 Counter (32-bit) */
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#define MCCHIPREG_TIMER4_COMP 0x38 /* Tick Timer 4 Compare (32-bit) */
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#define MCCHIPREG_TIMER4_CNTR 0x3c /* Tick Timer 4 Counter (32-bit) */
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#define MCCHIPREG_BUS_CLOCK 0x40 /* Bus Clock */
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#define MCCHIPREG_EPROM_TIMING 0x41 /* EPROM Access Time Control */
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#define MCCHIPREG_FLASH_TIMING 0x42 /* FLASH Access Time Control */
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#define MCCHIPREG_ABORT_ICSR 0x43 /* ABORT Switch Interrupt Control */
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#define MCCHIPREG_RESET_CONTROL 0x44 /* Reset Switch Control */
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#define MCCHIPREG_WDOG_CONTROL 0x45 /* Watchdog Timer Control */
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#define MCCHIPREG_TIMEBASE_SEL 0x46 /* Access & Watchdog Timebase Select */
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#define MCCHIPREG_DRAM_CONTROL 0x48 /* Parity DRAM Control */
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#define MCCHIPREG_MPU_STATUS 0x4a /* MPU Status */
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#define MCCHIPREG_PRESCALER 0x4c /* Prescaler Count Register (32-bits) */
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/*
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* PCCchip2's register size is 0x40. MCchip's is 0x50. Plump for the latter.
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*/
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#define PCC2REG_SIZE 0x50
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/*
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* Convenience macroes for accessing the PCCChip2's registers
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* through bus_space.
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*/
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#define pcc2_reg_read(sc,r) \
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bus_space_read_1((sc)->sc_bust, (sc)->sc_bush, (r))
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#define pcc2_reg_read16(sc,r) \
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bus_space_read_2((sc)->sc_bust, (sc)->sc_bush, (r))
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#define pcc2_reg_read32(sc,r) \
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bus_space_read_4((sc)->sc_bust, (sc)->sc_bush, (r))
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#define pcc2_reg_write(sc,r,v) \
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bus_space_write_1((sc)->sc_bust, (sc)->sc_bush, (r), (v))
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#define pcc2_reg_write16(sc,r,v) \
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bus_space_write_2((sc)->sc_bust, (sc)->sc_bush, (r), (v))
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#define pcc2_reg_write32(sc,r,v) \
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bus_space_write_4((sc)->sc_bust, (sc)->sc_bush, (r), (v))
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/*
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* We use the interrupt vector bases suggested in the Motorola Docs...
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* The first is written to the PCCChip2 for interrupt sources under
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* its control. The second is written to the CD2401's Local Interrupt
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* Vector Register. Thus, we don't use the Auto-Vector facilities
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* for the CD2401, as recommended in the PCCChip2 Programmer's Guide.
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* The third is used as a base for the ZS85230 serial chips on mvme162.
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*/
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#define PCCTWO_VECBASE 0x50
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#define PCCTWO_SCC_VECBASE 0x5c
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#define MCCHIP_ZS_VECBASE 0x5c
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/*
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* PCCchip2 Vector Encoding (Offsets from PCCTWO_VECBASE)
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* The order 0x0 -> 0xf also indicates priority, with 0x0 lowest.
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*/
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#define PCCTWOV_PRT_BUSY 0x0 /* Printer Port 'BSY' */
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#define PCCTWOV_PRT_PE 0x1 /* Printer Port 'PE' (Paper Empty) */
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#define PCCTWOV_PRT_SELECT 0x2 /* Printer Port 'SELECT' */
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#define PCCTWOV_PRT_FAULT 0x3 /* Printer Port 'FAULT' */
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#define PCCTWOV_PRT_ACK 0x4 /* Printer Port 'ACK' */
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#define PCCTWOV_SCSI 0x5 /* SCSI Interrupt */
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#define PCCTWOV_LANC_ERR 0x6 /* LAN Controller Error */
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#define PCCTWOV_LANC_IRQ 0x7 /* LAN Controller Interrupt */
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#define PCCTWOV_TIMER2 0x8 /* Tick Timer 2 Interrupt */
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#define PCCTWOV_TIMER1 0x9 /* Tick Timer 1 Interrupt */
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#define PCCTWOV_GPIO 0xa /* General Purpose Input Interrupt */
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#define PCCTWOV_SCC_RX_EXCEP 0xc /* SCC Receive Exception */
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#define PCCTWOV_SCC_MODEM 0xd /* SCC Modem (Non-Auto-vector mode) */
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#define PCCTWOV_SCC_TX 0xe /* SCC Tx (Non-Auto-vector mode) */
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#define PCCTWOV_SCC_RX 0xf /* SCC Rx (Non-Auto-vector mode) */
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#define PCCTWOV_MAX 16
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/*
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* MCchip-specific Vector Encoding (Offsets from PCCTWO_VECBASE)
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*/
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#define MCCHIPV_TIMER4 0x3 /* Tick Timer 4 Interrupt */
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#define MCCHIPV_TIMER3 0x4 /* Tick Timer 3 Interrupt */
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#define MCCHIPV_PARITY_ERR 0xb /* Parity DRAM Error Exception */
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#define MCCHIPV_ZS0 0xc /* First ZS85230 Interrupt Vector */
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#define MCCHIPV_ZS1 0xc /* Second ZS85230 Interrupt Vector */
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#define MCCHIPV_ABORT 0xe /* Abort Switch */
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/*
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* How to identify the PCCchip2 from an MCchip
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*/
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#define PCCTWO_CHIP_ID_PCC2 0x20
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#define PCCTWO_CHIP_ID_MCCHIP 0x84
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/*
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* Bit Values for the General Control Register (PCC2REG_GENERAL_CONTROL)
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*/
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#define PCCTWO_GEN_CTRL_FAST (1u<<0) /* BBRAM Speed Control */
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#define PCCTWO_GEN_CTRL_MIEN (1u<<1) /* Master Interrupt Enable */
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#define PCCTWO_GEN_CTRL_C040 (1u<<2) /* Set when CPU is mc68k family */
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#define PCCTWO_GEN_CTRL_DR0 (1u<<3) /* Download ROM at 0 (mvme166 only) */
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/*
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* Calculate the Prescaler Adjust value for a given
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* value of BCLK in MHz. (PCC2REG_PRESCALE_ADJUST)
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*/
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#define PCCTWO_PRES_ADJ(mhz) (256 - (mhz))
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/*
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* Calculate the Tick Timer Compare register value for
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* a given number of micro-seconds. With the PCCChip2,
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* this is simple since the Tick Counters already have
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* a 1uS period. (PCC2REG_TIMER[12]_COMPARE)
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*/
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#define PCCTWO_US2LIM(us) (us)
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#define PCCTWO_LIM2US(lim) (lim)
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/*
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* The Tick Timer Control Registers (PCC2REG_TIMER[12]_CONTROL)
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*/
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#define PCCTWO_TT_CTRL_CEN (1u<<0) /* Counter Enable */
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#define PCCTWO_TT_CTRL_COC (1u<<1) /* Clear On Compare */
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#define PCCTWO_TT_CTRL_COVF (1u<<2) /* Clear Overflow Counter */
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#define PCCTWO_TT_CTRL_OVF(r) ((r)>>4)/* Value of the Overflow Counter */
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/*
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* All the Interrupt Control Registers (PCC2REG_*_ICSR) on the PCCChip2
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* mostly share the same basic layout. These are defined as follows:
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*/
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#define PCCTWO_ICR_LEVEL_MASK 0x7 /* Mask for the interrupt level */
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#define PCCTWO_ICR_ICLR (1u<<3) /* Clear Int. (edge-sensitive mode) */
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#define PCCTWO_ICR_AVEC (1u<<3) /* Enable Auto-Vector Mode */
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#define PCCTWO_ICR_IEN (1u<<4) /* Interrupt Enable */
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#define PCCTWO_ICR_INT (1u<<5) /* Interrupt Active */
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#define PCCTWO_ICR_LEVEL (0u<<6) /* Level Triggered */
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#define PCCTWO_ICR_EDGE (1u<<6) /* Edge Triggered */
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#define PCCTWO_ICR_RISE_HIGH (0u<<7) /* Polarity: Rising Edge or Hi Level */
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#define PCCTWO_ICR_FALL_LOW (1u<<7) /* Polarity: Falling Edge or Lo Level */
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#define PCCTWO_ICR_SC_RD(r) ((r)>>6)/* Get Snoop Control Bits */
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#define PCCTWO_ICR_SC_WR(r) ((r)<<6)/* Write Snoop Control Bits */
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/*
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* Most of the Error Status Registers (PCC2REG_*_ERR_STATUS) mostly
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* follow the same layout. These error registers are used when a
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* device (eg. SCC, LANC) is mastering the PCCChip2's local bus (for
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* example, performing a DMA) and some error occurs. The bits are
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* defined as follows:
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*/
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#define PCCTWO_ERR_SR_SCLR (1u<<0) /* Clear Error Status */
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#define PCCTWO_ERR_SR_LTO (1u<<1) /* Local Bus Timeout */
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#define PCCTWO_ERR_SR_EXT (1u<<2) /* External (VMEbus) Error */
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#define PCCTWO_ERR_SR_PRTY (1u<<3) /* DRAM Parity Error */
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#define PCCTWO_ERR_SR_RTRY (1u<<4) /* Retry Required */
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#define PCCTWO_ERR_SR_MASK 0x0Eu
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/*
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* General Purpose Input/Output Pin Control Register
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* (PCC2REG_GPIO_CONTROL)
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*/
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#define PCCTWO_GPIO_CTRL_GPO (1u<<0) /* Controls the GP Output Pin */
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#define PCCTWO_GPIO_CTRL_GPOE (1u<<1) /* General Purpose Output Enable */
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#define PCCTWO_GPIO_CTRL_GPI (1u<<3) /* The current state of the GP Input */
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/*
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* Printer Input Status Register (PCC2REG_PRT_INPUT_STATUS)
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*/
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#define PCCTWO_PRT_IN_SR_BSY (1u<<0) /* State of printer's BSY Input */
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#define PCCTWO_PRT_IN_SR_PE (1u<<1) /* State of printer's PE Input */
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#define PCCTWO_PRT_IN_SR_SEL (1u<<2) /* State of printer's SELECT Input */
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#define PCCTWO_PRT_IN_SR_FLT (1u<<3) /* State of printer's FAULT Input */
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#define PCCTWO_PRT_IN_SR_ACK (1u<<4) /* State of printer's ACK Input */
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#define PCCTWO_PRT_IN_SR_PINT (1u<<7) /* Printer Interrupt Status */
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/*
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* Printer Port Control Register (PCC2REG_PRT_CONTROL)
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*/
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#define PCCTWO_PRT_CTRL_MAN (1u<<0) /* Manual Strobe Control */
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#define PCCTWO_PRT_CTRL_FAST (1u<<1) /* Fast Auto Strobe */
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#define PCCTWO_PRT_CTRL_STB (1u<<2) /* Strobe Pin, in manual control mode */
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#define PCCTWO_PRT_CTRL_INP (1u<<3) /* Printer Input Prime */
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#define PCCTWO_PRT_CTRL_DOEN (1u<<4) /* Printer Data Output Enable */
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#endif /* _MVME_PCCTWOREG_H */
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