185 lines
4.8 KiB
C
185 lines
4.8 KiB
C
/* $NetBSD: mii_bitbang.c,v 1.5 2001/11/13 07:41:37 lukem Exp $ */
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/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Common module for bit-bang'ing the MII.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: mii_bitbang.c,v 1.5 2001/11/13 07:41:37 lukem Exp $");
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#include <sys/param.h>
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#include <sys/device.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/mii_bitbang.h>
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void mii_bitbang_sync(struct device *, mii_bitbang_ops_t);
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void mii_bitbang_sendbits(struct device *, mii_bitbang_ops_t,
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u_int32_t, int);
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#define WRITE(x) \
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do { \
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ops->mbo_write(sc, (x)); \
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delay(1); \
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} while (/* CONSTCOND */ 0)
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#define READ ops->mbo_read(sc)
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#define MDO ops->mbo_bits[MII_BIT_MDO]
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#define MDI ops->mbo_bits[MII_BIT_MDI]
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#define MDC ops->mbo_bits[MII_BIT_MDC]
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#define MDIRPHY ops->mbo_bits[MII_BIT_DIR_HOST_PHY]
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#define MDIRHOST ops->mbo_bits[MII_BIT_DIR_PHY_HOST]
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/*
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* mii_bitbang_sync:
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*
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* Synchronize the MII.
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*/
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void
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mii_bitbang_sync(struct device *sc, mii_bitbang_ops_t ops)
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{
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int i;
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u_int32_t v;
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v = MDIRPHY | MDO;
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WRITE(v);
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for (i = 0; i < 32; i++) {
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WRITE(v | MDC);
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WRITE(v);
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}
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}
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/*
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* mii_bitbang_sendbits:
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*
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* Send a series of bits to the MII.
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*/
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void
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mii_bitbang_sendbits(struct device *sc, mii_bitbang_ops_t ops, uint32_t data,
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int nbits)
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{
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int i;
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u_int32_t v;
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v = MDIRPHY;
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WRITE(v);
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for (i = 1 << (nbits - 1); i != 0; i >>= 1) {
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if (data & i)
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v |= MDO;
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else
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v &= ~MDO;
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WRITE(v);
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WRITE(v | MDC);
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WRITE(v);
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}
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}
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/*
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* mii_bitbang_readreg:
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*
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* Read a PHY register by bit-bang'ing the MII.
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*/
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int
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mii_bitbang_readreg(struct device *sc, mii_bitbang_ops_t ops, int phy, int reg)
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{
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int val = 0, err = 0, i;
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mii_bitbang_sync(sc, ops);
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mii_bitbang_sendbits(sc, ops, MII_COMMAND_START, 2);
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mii_bitbang_sendbits(sc, ops, MII_COMMAND_READ, 2);
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mii_bitbang_sendbits(sc, ops, phy, 5);
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mii_bitbang_sendbits(sc, ops, reg, 5);
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/* Switch direction to PHY->host, without a clock transition. */
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WRITE(MDIRHOST);
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/* Turnaround clock. */
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WRITE(MDIRHOST | MDC);
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WRITE(MDIRHOST);
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/* Check for error. */
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err = READ & MDI;
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/* Idle clock. */
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WRITE(MDIRHOST | MDC);
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WRITE(MDIRHOST);
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for (i = 0; i < 16; i++) {
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val <<= 1;
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/* Read data prior to clock low-high transition. */
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if (err == 0 && (READ & MDI) != 0)
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val |= 1;
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WRITE(MDIRHOST | MDC);
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WRITE(MDIRHOST);
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}
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/* Set direction to host->PHY, without a clock transition. */
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WRITE(MDIRPHY);
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return (err ? 0 : val);
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}
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/*
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* mii_bitbang_writereg:
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*
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* Write a PHY register by bit-bang'ing the MII.
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*/
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void
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mii_bitbang_writereg(struct device *sc, mii_bitbang_ops_t ops, int phy,
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int reg, int val)
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{
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mii_bitbang_sync(sc, ops);
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mii_bitbang_sendbits(sc, ops, MII_COMMAND_START, 2);
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mii_bitbang_sendbits(sc, ops, MII_COMMAND_WRITE, 2);
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mii_bitbang_sendbits(sc, ops, phy, 5);
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mii_bitbang_sendbits(sc, ops, reg, 5);
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mii_bitbang_sendbits(sc, ops, MII_COMMAND_ACK, 2);
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mii_bitbang_sendbits(sc, ops, val, 16);
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WRITE(MDIRPHY);
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}
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