416 lines
10 KiB
C
416 lines
10 KiB
C
/* $NetBSD: pci.c,v 1.7 2008/04/28 20:23:34 martin Exp $ */
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/*-
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* Copyright (c) 2007 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Tohru Nishimura.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <lib/libsa/stand.h>
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/*
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* "Map B" layout
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*
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* practice direct mode configuration scheme with CONFIG_ADDR
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* (0xfec0'0000) and CONFIG_DATA (0xfee0'0000).
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*/
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#define PCI_MEMBASE 0x80000000
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#define PCI_MEMLIMIT 0xfbffffff /* EUMB is next to this */
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#define PCI_IOBASE 0x00001000 /* reserves room for via 686B */
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#define PCI_IOLIMIT 0x000fffff
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#define CONFIG_ADDR 0xfec00000
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#define CONFIG_DATA 0xfee00000
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#define MAXNDEVS 32
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#include "globals.h"
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static unsigned cfgread(int, int, int, int);
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static void cfgwrite(int, int, int, int, unsigned);
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static void _buswalk(int,
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int (*)(int, int, int, unsigned long), unsigned long);
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static int _pcilookup(int,
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int (*)(int, int, int, unsigned long), unsigned long,
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unsigned [][2], int, int);
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static int deviceinit(int, int, int, unsigned long);
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static void memassign(int, int, int);
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static int devmatch(int, int, int, unsigned long);
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static int clsmatch(int, int, int, unsigned long);
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unsigned memstart, memlimit;
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unsigned iostart, iolimit;
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unsigned maxbus;
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void
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pcisetup()
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{
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memstart = PCI_MEMBASE;
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memlimit = PCI_MEMLIMIT;
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iostart = PCI_IOBASE;
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iolimit = PCI_IOLIMIT;
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maxbus = 0;
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(void)_buswalk(0, deviceinit, 0UL);
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}
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int
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pcifinddev(vend, prod, tag)
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unsigned vend, prod;
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unsigned *tag;
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{
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unsigned pciid, target[1][2];
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pciid = PCI_DEVICE(vend, prod);
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if (_pcilookup(0, devmatch, pciid, target, 0, 1)) {
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*tag = target[0][1];
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return 0;
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}
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*tag = ~0;
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return -1;
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}
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int
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pcilookup(type, list, max)
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unsigned type;
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unsigned list[][2];
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int max;
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{
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return _pcilookup(0, clsmatch, type, list, 0, max);
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}
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unsigned
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pcimaketag(b, d, f)
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int b, d, f;
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{
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return (1U << 31) | (b << 16) | (d << 11) | (f << 8);
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}
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void
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pcidecomposetag(tag, b, d, f)
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unsigned tag;
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int *b, *d, *f;
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{
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if (b != NULL)
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*b = (tag >> 16) & 0xff;
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if (d != NULL)
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*d = (tag >> 11) & 0x1f;
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if (f != NULL)
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*f = (tag >> 8) & 0x7;
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return;
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}
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unsigned
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pcicfgread(tag, off)
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unsigned tag;
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int off;
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{
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unsigned cfg;
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cfg = tag | (off &~ 03);
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iohtole32(CONFIG_ADDR, cfg);
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return iole32toh(CONFIG_DATA);
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}
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void
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pcicfgwrite(tag, off, val)
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unsigned tag;
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int off;
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unsigned val;
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{
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unsigned cfg;
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cfg = tag | (off &~ 03);
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iohtole32(CONFIG_ADDR, cfg);
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iohtole32(CONFIG_DATA, val);
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}
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static unsigned
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cfgread(b, d, f, off)
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int b, d, f, off;
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{
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unsigned cfg;
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off &= ~03;
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cfg = (1U << 31) | (b << 16) | (d << 11) | (f << 8) | off | 0;
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iohtole32(CONFIG_ADDR, cfg);
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return iole32toh(CONFIG_DATA);
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}
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static void
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cfgwrite(b, d, f, off, val)
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int b, d, f, off;
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unsigned val;
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{
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unsigned cfg;
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off &= ~03;
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cfg = (1U << 31) | (b << 16) | (d << 11) | (f << 8) | off | 0;
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iohtole32(CONFIG_ADDR, cfg);
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iohtole32(CONFIG_DATA, val);
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}
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static void
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_buswalk(bus, proc, data)
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int bus;
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int (*proc)(int, int, int, unsigned long);
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unsigned long data;
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{
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int device, function, nfunctions;
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unsigned pciid, bhlcr;
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for (device = 0; device < MAXNDEVS; device++) {
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pciid = cfgread(bus, device, 0, PCI_ID_REG);
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if (PCI_VENDOR(pciid) == PCI_VENDOR_INVALID)
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continue;
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if (PCI_VENDOR(pciid) == 0)
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continue;
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bhlcr = cfgread(bus, device, 0, PCI_BHLC_REG);
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nfunctions = (PCI_HDRTYPE_MULTIFN(bhlcr)) ? 8 : 1;
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for (function = 0; function < nfunctions; function++) {
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pciid = cfgread(bus, device, function, PCI_ID_REG);
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if (PCI_VENDOR(pciid) == PCI_VENDOR_INVALID)
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continue;
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if (PCI_VENDOR(pciid) == 0)
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continue;
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if ((*proc)(bus, device, function, data) != 0)
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goto out; /* early exit */
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}
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}
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out:;
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}
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static int
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deviceinit(bus, dev, func, data)
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int bus, dev, func;
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unsigned long data;
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{
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unsigned val;
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/* 0x00 */
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printf("%02d:%02d:%02d:", bus, dev, func);
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val = cfgread(bus, dev, func, 0x00);
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printf(" chip %04x.%04x", val & 0xffff, val>>16);
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val = cfgread(bus, dev, func, 0x2c);
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printf(" card %04x.%04x", val & 0xffff, val>>16);
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val = cfgread(bus, dev, func, 0x08);
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printf(" rev %02x class %02x.%02x.%02x",
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val & 0xff, (val>>24), (val>>16) & 0xff, (val>>8) & 0xff);
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val = cfgread(bus, dev, func, 0x0c);
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printf(" hdr %02x\n", (val>>16) & 0xff);
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/* 0x04 */
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val = cfgread(bus, dev, func, 0x04);
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val |= 0xffff0107; /* enable IO,MEM,MASTER,SERR */
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cfgwrite(bus, dev, func, 0x04, val);
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/* 0x0c */
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val = 0x80 << 8 | 0x08 /* 32B cache line */;
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cfgwrite(bus, dev, func, 0x0c, val);
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#if 1
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/* skip IDE controller BAR assignment */
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val = cfgread(bus, dev, func, PCI_CLASS_REG);
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if ((val >> 16) == PCI_CLASS_IDE)
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return 0;
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#endif
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memassign(bus, dev, func);
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/* descending toward PCI-PCI bridge */
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if ((cfgread(bus, dev, func, 0x08) >> 16) == PCI_CLASS_PPB) {
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unsigned new;
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/* 0x18 */
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new = (maxbus += 1);
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val = (0xff << 16) | (new << 8) | bus;
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cfgwrite(bus, dev, func, 0x18, val);
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/* 0x1c and 0x30 */
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val = (iostart + (0xfff)) & ~0xfff; /* 4KB boundary */
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iostart = val;
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val = 0xffff0000 | (iolimit & 0xf000) | (val & 0xf000) >> 8;
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cfgwrite(bus, dev, func, 0x1c, val);
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val = (iolimit & 0xffff0000) | (val & 0xffff0000) >> 16;
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cfgwrite(bus, dev, func, 0x30, val);
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/* 0x20 */
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val = (memstart + 0xfffff) &~ 0xfffff; /* 1MB boundary */
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memstart = val;
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val = (memlimit & 0xffff0000) | (val & 0xffff0000) >> 16;
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cfgwrite(bus, dev, func, 0x20, val);
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/* redo 0x04 */
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val = cfgread(bus, dev, func, 0x04);
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val |= 0xffff0107;
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cfgwrite(bus, dev, func, 0x04, val);
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_buswalk(new, deviceinit, data);
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/* adjust 0x18 */
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val = cfgread(bus, dev, func, 0x18);
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val = (maxbus << 16) | (val & 0xffff);
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cfgwrite(bus, dev, func, 0x18, val);
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}
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return 0;
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}
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static void
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memassign(bus, dev, func)
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int bus, dev, func;
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{
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unsigned val, maxbar, mapr, req, mapbase, size;
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val = cfgread(bus, dev, func, 0x0c);
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switch (PCI_HDRTYPE_TYPE(val)) {
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case 0:
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maxbar = 0x10 + 6 * 4; break;
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case 1:
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maxbar = 0x10 + 2 * 4; break;
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default:
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maxbar = 0x10 + 1 * 4; break;
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}
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for (mapr = 0x10; mapr < maxbar; mapr += 4) {
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cfgwrite(bus, dev, func, mapr, 0xffffffff);
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val = cfgread(bus, dev, func, mapr);
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if (val & 01) {
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/* PCI IO space */
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req = ~(val & 0xfffffffc) + 1;
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if (req & (req - 1)) /* power of 2 */
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continue;
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if (req == 0) /* ever exists */
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continue;
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size = (req > 0x10) ? req : 0x10;
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mapbase = (iostart + size - 1) & ~(size - 1);
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if (mapbase + size > iolimit)
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continue;
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iostart = mapbase + size;
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/* establish IO space */
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cfgwrite(bus, dev, func, mapr, mapbase | 01);
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}
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else {
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/* PCI memory space */
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req = ~(val & 0xfffffff0) + 1;
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if (req & (req - 1)) /* power of 2 */
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continue;
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if (req == 0) /* ever exists */
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continue;
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val &= 0x6;
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if (val == 2 || val == 6)
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continue;
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size = (req > 0x1000) ? req : 0x1000;
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mapbase = (memstart + size - 1) & ~(size - 1);
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if (mapbase + size > memlimit)
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continue;
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memstart = mapbase + size;
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/* establish memory space */
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cfgwrite(bus, dev, func, mapr, mapbase);
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if (val == 4) {
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mapr += 4;
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cfgwrite(bus, dev, func, mapr, 0);
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}
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}
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printf("%s base %x size %x\n", (val & 01) ? "i/o" : "mem", mapbase, size);
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}
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}
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static int
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devmatch(bus, dev, func, data)
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int bus, dev, func;
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unsigned long data;
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{
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unsigned pciid;
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pciid = cfgread(bus, dev, func, PCI_ID_REG);
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return (pciid == (unsigned)data);
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}
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static int
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clsmatch(bus, dev, func, data)
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int bus, dev, func;
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unsigned long data;
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{
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unsigned class;
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class = cfgread(bus, dev, func, PCI_CLASS_REG);
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return ((class >> 16) == (unsigned)data);
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}
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static int
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_pcilookup(bus, match, data, list, index, limit)
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int bus;
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int (*match)(int, int, int, unsigned long);
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unsigned long data;
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unsigned list[][2];
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int index, limit;
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{
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int device, function, nfuncs;
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unsigned pciid, bhlcr, class;
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for (device = 0; device < MAXNDEVS; device++) {
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pciid = cfgread(bus, device, 0, PCI_ID_REG);
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if (PCI_VENDOR(pciid) == PCI_VENDOR_INVALID)
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continue;
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if (PCI_VENDOR(pciid) == 0)
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continue;
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class = cfgread(bus, device, 0, PCI_CLASS_REG);
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if ((class >> 16) == PCI_CLASS_PPB) {
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/* exploring bus beyond PCI-PCI bridge */
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index = _pcilookup(bus + 1,
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match, data, list, index, limit);
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if (index >= limit)
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goto out;
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continue;
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}
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bhlcr = cfgread(bus, device, 0, PCI_BHLC_REG);
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nfuncs = (PCI_HDRTYPE_MULTIFN(bhlcr)) ? 8 : 1;
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for (function = 0; function < nfuncs; function++) {
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pciid = cfgread(bus, device, function, PCI_ID_REG);
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if (PCI_VENDOR(pciid) == PCI_VENDOR_INVALID)
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continue;
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if (PCI_VENDOR(pciid) == 0)
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continue;
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if ((*match)(bus, device, function, data)) {
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list[index][0] = pciid;
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list[index][1] =
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pcimaketag(bus, device, function);
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index += 1;
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if (index >= limit)
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goto out;
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}
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}
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}
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out:
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return index;
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}
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