147 lines
5.5 KiB
C
147 lines
5.5 KiB
C
/* $NetBSD: algor_p5064reg.h,v 1.2 2002/02/20 01:34:19 simonb Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Memory map and register definitions for the Algorithmics P-5064.
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*/
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#define P5064_MEMORY 0x00000000UL /* onboard DRAM memory */
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/* 256 MB */
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#define P5064_ISAMEM 0x10000000UL /* ISA window of PCI memory */
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/* 8MB */
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#define P5064_PCIMEM 0x11000000UL /* PCI memory window */
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/* 112MB */
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#define P5064_PCIIO 0x1d000000UL /* PCI I/O window */
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/* 16MB */
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#define P5064_PCICFG 0x1ee00000UL /* PCI config space */
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/* 1MB */
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#define P5064_V360EPC 0x1ef00000UL /* V360EPC PCI controller */
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/* 64KB */
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#define P5064_CFGBOOT_W 0x1f800000UL /* configured bootstrap (W) */
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/* 512KB */
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#define P5064_SOCKET_W 0x1f900000UL /* socket EPROM (W) */
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/* 512KB */
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#define P5064_FLASH_W 0x1fa00000UL /* flash (W) */
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/* 1MB */
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#define P5064_CFBOOT 0x1fc00000UL /* configured bootstrap */
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/* 512KB */
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#define P5064_SOCKET 0x1fd00000UL /* socket EPROM */
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/* 512KB */
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#define P5064_FLASH 0x1fe00000UL /* flash */
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/* 1MB */
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#define P5064_LED0 0x1ff00000UL /* LED (1reg) */
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#define P5064_LED1 0x1ff20010UL /* LED (4reg) */
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#define P5064_LCD 0x1ff30000UL /* LCD display */
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#define P5064_Z80GPIO 0x1ff40000UL /* Z80 GPIO (rev B only) */
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#define P5064_Z80GPIO_IACK 0x1ff50000UL /* intr. ack. for Z80 */
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#define P5064_DBG_UART 0x1ff60000UL /* UART on debug board */
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#define P5064_LOCINT 0x1ff90000UL /* local interrupts */
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#define P5064_PANIC 0x1ff90004UL /* panic interrupts */
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#define P5064_PCIINT 0x1ff90008UL /* PCI interrupts */
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#define P5064_ISAINT 0x1ff9000cUL /* ISA interrupts */
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#define P5064_XBAR0 0x1ff90010UL /* Int. xbar 0 */
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#define P5064_XBAR1 0x1ff90014UL /* Int. xbar 1 */
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#define P5064_XBAR2 0x1ff90018UL /* Int. xbar 2 */
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#define P5064_XBAR3 0x1ff9001cUL /* Int. xbar 3 */
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#define P5064_XBAR4 0x1ff90020UL /* Int. xbar 4 */
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#define P5064_KBDINT 0x1ff90024UL /* keyboard interrupts */
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#define P5064_LOGICREV 0x1ff9003cUL /* logic revision */
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#define P5064_CFG0 0x1ffa0000UL /* board configuration 0 */
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#define P5064_CFG1 0x1ffb0000UL /* board configuration 1 */
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#define P5064_DRAMCFG 0x1ffc0000UL /* DRAM configuration */
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#define P5064_BOARDREV 0x1ffd0000UL /* board revision */
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#define P5064_PCIMEM_HI 0x20000000UL /* PCI memory high window */
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/* 3.5GB */
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/* P5064_LOCINT */
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#define LOCINT_PCIBR 0x01
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#define LOCINT_FLP 0x02
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#define LOCINT_MKBD 0x04
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#define LOCINT_COM1 0x08
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#define LOCINT_COM2 0x10
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#define LOCINT_CENT 0x20
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#define LOCINT_RTC 0x80
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/* P5064_PANIC */
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#define PANIC_DEBUG 0x01
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#define PANIC_PFAIL 0x02
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#define PANIC_BERR 0x04
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#define PANIC_ISANMI 0x08
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#define PANIC_IOPERR 0x10
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#define PANIC_CENT 0x20
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#define PANIC_EWAKE 0x40
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#define PANIC_ECODERR 0x80
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/* P5064_PCIINT */
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#define PCIINT_EMDINT 0x01
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#define PCIINT_ETH 0x02
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#define PCIINT_SCSI 0x04
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#define PCIINT_USB 0x08
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#define PCIINT_PCI0 0x10
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#define PCIINT_PCI1 0x20
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#define PCIINT_PCI2 0x40
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#define PCIINT_PCI3 0x80
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/* P5064_ISAINT */
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#define ISAINT_ISABR 0x01
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#define ISAINT_IDE0 0x02
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#define ISAINT_IDE1 0x04
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/* P5064_KBDINT */
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#define KBDINT_KBD 0x01
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#define KBDINT_MOUSE 0x02
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/*
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* The Algorithmics PMON initializes two DMA windows:
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*
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* THE MANUAL CLAIMS THIS:
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* PCI 0080.0000 -> Phys 0080.0000 (8MB)
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*
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* THE PMON FIRMWARE DOES THIS:
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* PCI 0080.0000 -> Phys 0000.0000 (8MB)
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*
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* PCI 8000.0000 -> Phys 0000.0000 (256MB)
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*/
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#define P5064_DMA_ISA_PCIBASE 0x00800000UL
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#define P5064_DMA_ISA_PHYSBASE 0x00000000UL
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#define P5064_DMA_ISA_SIZE (8 * 1024 * 1024)
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#define P5064_DMA_PCI_PCIBASE 0x80000000UL
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#define P5064_DMA_PCI_PHYSBASE 0x00000000UL
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#define P5064_DMA_PCI_SIZE (256 * 1024 * 1024)
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