718 lines
19 KiB
C
718 lines
19 KiB
C
/* $NetBSD: pcs_bus_io_common.c,v 1.14 1996/12/02 22:19:35 cgd Exp $ */
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/*
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* Copyright (c) 1995, 1996 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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/*
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* Common PCI Chipset "bus I/O" functions, for chipsets which have to
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* deal with only a single PCI interface chip in a machine.
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*
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* uses:
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* CHIP name of the 'chip' it's being compiled for.
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* CHIP_IO_BASE Sparse I/O space base to use.
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*/
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#include <sys/extent.h>
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#define __C(A,B) __CONCAT(A,B)
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#define __S(S) __STRING(S)
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/* mapping/unmapping */
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int __C(CHIP,_io_map) __P((void *, bus_addr_t, bus_size_t, int,
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bus_space_handle_t *));
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void __C(CHIP,_io_unmap) __P((void *, bus_space_handle_t,
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bus_size_t));
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int __C(CHIP,_io_subregion) __P((void *, bus_space_handle_t,
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bus_size_t, bus_size_t, bus_space_handle_t *));
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/* allocation/deallocation */
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int __C(CHIP,_io_alloc) __P((void *, bus_addr_t, bus_addr_t,
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bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *,
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bus_space_handle_t *));
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void __C(CHIP,_io_free) __P((void *, bus_space_handle_t,
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bus_size_t));
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/* barrier */
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inline void __C(CHIP,_io_barrier) __P((void *, bus_space_handle_t,
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bus_size_t, bus_size_t, int));
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/* read (single) */
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inline u_int8_t __C(CHIP,_io_read_1) __P((void *, bus_space_handle_t,
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bus_size_t));
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inline u_int16_t __C(CHIP,_io_read_2) __P((void *, bus_space_handle_t,
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bus_size_t));
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inline u_int32_t __C(CHIP,_io_read_4) __P((void *, bus_space_handle_t,
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bus_size_t));
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inline u_int64_t __C(CHIP,_io_read_8) __P((void *, bus_space_handle_t,
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bus_size_t));
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/* read multiple */
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void __C(CHIP,_io_read_multi_1) __P((void *, bus_space_handle_t,
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bus_size_t, u_int8_t *, bus_size_t));
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void __C(CHIP,_io_read_multi_2) __P((void *, bus_space_handle_t,
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bus_size_t, u_int16_t *, bus_size_t));
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void __C(CHIP,_io_read_multi_4) __P((void *, bus_space_handle_t,
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bus_size_t, u_int32_t *, bus_size_t));
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void __C(CHIP,_io_read_multi_8) __P((void *, bus_space_handle_t,
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bus_size_t, u_int64_t *, bus_size_t));
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/* read region */
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void __C(CHIP,_io_read_region_1) __P((void *, bus_space_handle_t,
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bus_size_t, u_int8_t *, bus_size_t));
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void __C(CHIP,_io_read_region_2) __P((void *, bus_space_handle_t,
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bus_size_t, u_int16_t *, bus_size_t));
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void __C(CHIP,_io_read_region_4) __P((void *, bus_space_handle_t,
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bus_size_t, u_int32_t *, bus_size_t));
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void __C(CHIP,_io_read_region_8) __P((void *, bus_space_handle_t,
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bus_size_t, u_int64_t *, bus_size_t));
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/* write (single) */
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inline void __C(CHIP,_io_write_1) __P((void *, bus_space_handle_t,
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bus_size_t, u_int8_t));
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inline void __C(CHIP,_io_write_2) __P((void *, bus_space_handle_t,
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bus_size_t, u_int16_t));
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inline void __C(CHIP,_io_write_4) __P((void *, bus_space_handle_t,
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bus_size_t, u_int32_t));
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inline void __C(CHIP,_io_write_8) __P((void *, bus_space_handle_t,
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bus_size_t, u_int64_t));
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/* write multiple */
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void __C(CHIP,_io_write_multi_1) __P((void *, bus_space_handle_t,
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bus_size_t, const u_int8_t *, bus_size_t));
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void __C(CHIP,_io_write_multi_2) __P((void *, bus_space_handle_t,
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bus_size_t, const u_int16_t *, bus_size_t));
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void __C(CHIP,_io_write_multi_4) __P((void *, bus_space_handle_t,
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bus_size_t, const u_int32_t *, bus_size_t));
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void __C(CHIP,_io_write_multi_8) __P((void *, bus_space_handle_t,
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bus_size_t, const u_int64_t *, bus_size_t));
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/* write region */
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void __C(CHIP,_io_write_region_1) __P((void *, bus_space_handle_t,
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bus_size_t, const u_int8_t *, bus_size_t));
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void __C(CHIP,_io_write_region_2) __P((void *, bus_space_handle_t,
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bus_size_t, const u_int16_t *, bus_size_t));
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void __C(CHIP,_io_write_region_4) __P((void *, bus_space_handle_t,
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bus_size_t, const u_int32_t *, bus_size_t));
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void __C(CHIP,_io_write_region_8) __P((void *, bus_space_handle_t,
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bus_size_t, const u_int64_t *, bus_size_t));
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/* set multiple */
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void __C(CHIP,_io_set_multi_1) __P((void *, bus_space_handle_t,
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bus_size_t, u_int8_t, bus_size_t));
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void __C(CHIP,_io_set_multi_2) __P((void *, bus_space_handle_t,
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bus_size_t, u_int16_t, bus_size_t));
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void __C(CHIP,_io_set_multi_4) __P((void *, bus_space_handle_t,
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bus_size_t, u_int32_t, bus_size_t));
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void __C(CHIP,_io_set_multi_8) __P((void *, bus_space_handle_t,
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bus_size_t, u_int64_t, bus_size_t));
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/* set region */
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void __C(CHIP,_io_set_region_1) __P((void *, bus_space_handle_t,
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bus_size_t, u_int8_t, bus_size_t));
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void __C(CHIP,_io_set_region_2) __P((void *, bus_space_handle_t,
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bus_size_t, u_int16_t, bus_size_t));
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void __C(CHIP,_io_set_region_4) __P((void *, bus_space_handle_t,
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bus_size_t, u_int32_t, bus_size_t));
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void __C(CHIP,_io_set_region_8) __P((void *, bus_space_handle_t,
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bus_size_t, u_int64_t, bus_size_t));
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/* copy */
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void __C(CHIP,_io_copy_1) __P((void *, bus_space_handle_t,
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bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t));
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void __C(CHIP,_io_copy_2) __P((void *, bus_space_handle_t,
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bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t));
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void __C(CHIP,_io_copy_4) __P((void *, bus_space_handle_t,
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bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t));
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void __C(CHIP,_io_copy_8) __P((void *, bus_space_handle_t,
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bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t));
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static long
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__C(CHIP,_io_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)];
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static struct alpha_bus_space __C(CHIP,_io_space) = {
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/* cookie */
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NULL,
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/* mapping/unmapping */
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__C(CHIP,_io_map),
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__C(CHIP,_io_unmap),
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__C(CHIP,_io_subregion),
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/* allocation/deallocation */
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__C(CHIP,_io_alloc),
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__C(CHIP,_io_free),
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/* barrier */
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__C(CHIP,_io_barrier),
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/* read (single) */
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__C(CHIP,_io_read_1),
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__C(CHIP,_io_read_2),
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__C(CHIP,_io_read_4),
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__C(CHIP,_io_read_8),
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/* read multiple */
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__C(CHIP,_io_read_multi_1),
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__C(CHIP,_io_read_multi_2),
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__C(CHIP,_io_read_multi_4),
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__C(CHIP,_io_read_multi_8),
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/* read region */
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__C(CHIP,_io_read_region_1),
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__C(CHIP,_io_read_region_2),
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__C(CHIP,_io_read_region_4),
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__C(CHIP,_io_read_region_8),
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/* write (single) */
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__C(CHIP,_io_write_1),
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__C(CHIP,_io_write_2),
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__C(CHIP,_io_write_4),
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__C(CHIP,_io_write_8),
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/* write multiple */
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__C(CHIP,_io_write_multi_1),
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__C(CHIP,_io_write_multi_2),
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__C(CHIP,_io_write_multi_4),
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__C(CHIP,_io_write_multi_8),
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/* write region */
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__C(CHIP,_io_write_region_1),
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__C(CHIP,_io_write_region_2),
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__C(CHIP,_io_write_region_4),
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__C(CHIP,_io_write_region_8),
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/* set multiple */
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__C(CHIP,_io_set_multi_1),
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__C(CHIP,_io_set_multi_2),
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__C(CHIP,_io_set_multi_4),
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__C(CHIP,_io_set_multi_8),
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/* set region */
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__C(CHIP,_io_set_region_1),
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__C(CHIP,_io_set_region_2),
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__C(CHIP,_io_set_region_4),
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__C(CHIP,_io_set_region_8),
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/* copy */
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__C(CHIP,_io_copy_1),
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__C(CHIP,_io_copy_2),
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__C(CHIP,_io_copy_4),
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__C(CHIP,_io_copy_8),
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};
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bus_space_tag_t
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__C(CHIP,_bus_io_init)(v)
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void *v;
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{
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bus_space_tag_t t = &__C(CHIP,_io_space);
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struct extent *ex;
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t->abs_cookie = v;
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/* XXX WE WANT EXTENT_NOCOALESCE, BUT WE CAN'T USE IT. XXX */
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ex = extent_create(__S(__C(CHIP,_bus_io)), 0x0UL, 0xffffffffUL,
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M_DEVBUF, (caddr_t)__C(CHIP,_io_ex_storage),
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sizeof(__C(CHIP,_io_ex_storage)), EX_NOWAIT);
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extent_alloc_region(ex, 0, 0xffffffffUL, EX_NOWAIT);
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#ifdef CHIP_IO_W1_BUS_START
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#ifdef EXTENT_DEBUG
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printf("io: freeing from 0x%lx to 0x%lx\n", CHIP_IO_W1_BUS_START(v),
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CHIP_IO_W1_BUS_END(v));
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#endif
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extent_free(ex, CHIP_IO_W1_BUS_START(v),
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CHIP_IO_W1_BUS_END(v) - CHIP_IO_W1_BUS_START(v) + 1, EX_NOWAIT);
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#endif
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#ifdef CHIP_IO_W2_BUS_START
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#ifdef EXTENT_DEBUG
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printf("io: freeing from 0x%lx to 0x%lx\n", CHIP_IO_W2_BUS_START(v),
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CHIP_IO_W2_BUS_END(v));
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#endif
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extent_free(ex, CHIP_IO_W2_BUS_START(v),
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CHIP_IO_W2_BUS_END(v) - CHIP_IO_W2_BUS_START(v) + 1, EX_NOWAIT);
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#endif
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#ifdef EXTENT_DEBUG
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extent_print(ex);
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#endif
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CHIP_IO_EXTENT(v) = ex;
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return (t);
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}
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int
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__C(CHIP,_io_map)(v, ioaddr, iosize, cacheable, iohp)
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void *v;
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bus_addr_t ioaddr;
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bus_size_t iosize;
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int cacheable;
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bus_space_handle_t *iohp;
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{
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int error;
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#ifdef EXTENT_DEBUG
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printf("io: allocating 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1);
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#endif
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error = extent_alloc_region(CHIP_IO_EXTENT(v), ioaddr, iosize,
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EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0));
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if (error) {
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#ifdef EXTENT_DEBUG
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printf("io: allocation failed (%d)\n", error);
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extent_print(CHIP_IO_EXTENT(v));
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#endif
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return (error);
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}
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#ifdef CHIP_IO_W1_BUS_START
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if (ioaddr >= CHIP_IO_W1_BUS_START(v) &&
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ioaddr <= CHIP_IO_W1_BUS_END(v)) {
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*iohp = (ALPHA_PHYS_TO_K0SEG(CHIP_IO_W1_SYS_START(v)) >> 5) +
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(ioaddr - CHIP_IO_W1_BUS_START(v));
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} else
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#endif
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#ifdef CHIP_IO_W2_BUS_START
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if (ioaddr >= CHIP_IO_W2_BUS_START(v) &&
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ioaddr <= CHIP_IO_W2_BUS_END(v)) {
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*iohp = (ALPHA_PHYS_TO_K0SEG(CHIP_IO_W2_SYS_START(v)) >> 5) +
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(ioaddr - CHIP_IO_W2_BUS_START(v));
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} else
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#endif
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{
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printf("\n");
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#ifdef CHIP_IO_W1_BUS_START
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printf("%s: window[1]=0x%lx-0x%lx\n",
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__S(__C(CHIP,_io_map)), CHIP_IO_W1_BUS_START(v),
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CHIP_IO_W1_BUS_END(v));
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#endif
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#ifdef CHIP_IO_W2_BUS_START
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printf("%s: window[2]=0x%lx-0x%lx\n",
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__S(__C(CHIP,_io_map)), CHIP_IO_W2_BUS_START(v),
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CHIP_IO_W2_BUS_END(v));
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#endif
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panic("%s: don't know how to map %lx",
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__S(__C(CHIP,_io_map)), ioaddr);
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}
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return (0);
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}
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void
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__C(CHIP,_io_unmap)(v, ioh, iosize)
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void *v;
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bus_space_handle_t ioh;
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bus_size_t iosize;
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{
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bus_addr_t ioaddr;
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int error;
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#ifdef EXTENT_DEBUG
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printf("io: freeing handle 0x%lx for 0x%lx\n", ioh, iosize);
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#endif
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ioh = ALPHA_K0SEG_TO_PHYS(ioh << 5) >> 5;
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#ifdef CHIP_IO_W1_BUS_START
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if ((ioh << 5) >= CHIP_IO_W1_SYS_START(v) &&
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(ioh << 5) <= CHIP_IO_W1_SYS_END(v)) {
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ioaddr = CHIP_IO_W1_BUS_START(v) +
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(ioh - (CHIP_IO_W1_SYS_START(v) >> 5));
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} else
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#endif
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#ifdef CHIP_IO_W2_BUS_START
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if ((ioh << 5) >= CHIP_IO_W2_SYS_START(v) &&
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(ioh << 5) <= CHIP_IO_W2_SYS_END(v)) {
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ioaddr = CHIP_IO_W2_BUS_START(v) +
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(ioh - (CHIP_IO_W2_SYS_START(v) >> 5));
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} else
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#endif
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{
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printf("\n");
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#ifdef CHIP_IO_W1_BUS_START
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printf("%s: sys window[1]=0x%lx-0x%lx\n",
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__S(__C(CHIP,_io_map)), CHIP_IO_W1_SYS_START(v),
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CHIP_IO_W1_SYS_END(v));
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#endif
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#ifdef CHIP_IO_W2_BUS_START
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printf("%s: sys window[2]=0x%lx-0x%lx\n",
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__S(__C(CHIP,_io_map)), CHIP_IO_W2_SYS_START(v),
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CHIP_IO_W2_SYS_END(v));
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#endif
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panic("%s: don't know how to unmap %lx",
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__S(__C(CHIP,_io_unmap)), (ioh << 5));
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}
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#ifdef EXTENT_DEBUG
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printf("io: freeing 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1);
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#endif
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error = extent_free(CHIP_IO_EXTENT(v), ioaddr, iosize,
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EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0));
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if (error) {
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printf("%s: WARNING: could not unmap 0x%lx-0x%lx (error %d)\n",
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__S(__C(CHIP,_io_unmap)), ioaddr, ioaddr + iosize - 1,
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error);
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#ifdef EXTENT_DEBUG
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extent_print(CHIP_IO_EXTENT(v));
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#endif
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}
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}
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int
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__C(CHIP,_io_subregion)(v, ioh, offset, size, nioh)
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void *v;
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bus_space_handle_t ioh, *nioh;
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bus_size_t offset, size;
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{
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*nioh = ioh + offset;
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return (0);
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}
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int
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__C(CHIP,_io_alloc)(v, rstart, rend, size, align, boundary, cacheable,
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addrp, bshp)
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void *v;
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bus_addr_t rstart, rend, *addrp;
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bus_size_t size, align, boundary;
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int cacheable;
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bus_space_handle_t *bshp;
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{
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/* XXX XXX XXX XXX XXX XXX */
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panic("%s not implemented", __S(__C(CHIP,_io_alloc)));
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}
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void
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__C(CHIP,_io_free)(v, bsh, size)
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void *v;
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bus_space_handle_t bsh;
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bus_size_t size;
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|
{
|
|
|
|
/* XXX XXX XXX XXX XXX XXX */
|
|
panic("%s not implemented", __S(__C(CHIP,_io_free)));
|
|
}
|
|
|
|
inline void
|
|
__C(CHIP,_io_barrier)(v, h, o, l, f)
|
|
void *v;
|
|
bus_space_handle_t h;
|
|
bus_size_t o, l;
|
|
int f;
|
|
{
|
|
|
|
if ((f & BUS_BARRIER_READ) != 0)
|
|
alpha_mb();
|
|
else if ((f & BUS_BARRIER_WRITE) != 0)
|
|
alpha_wmb();
|
|
}
|
|
|
|
inline u_int8_t
|
|
__C(CHIP,_io_read_1)(v, ioh, off)
|
|
void *v;
|
|
bus_space_handle_t ioh;
|
|
bus_size_t off;
|
|
{
|
|
register bus_space_handle_t tmpioh;
|
|
register u_int32_t *port, val;
|
|
register u_int8_t rval;
|
|
register int offset;
|
|
|
|
alpha_mb();
|
|
|
|
tmpioh = ioh + off;
|
|
offset = tmpioh & 3;
|
|
port = (u_int32_t *)((tmpioh << 5) | (0 << 3));
|
|
val = *port;
|
|
rval = ((val) >> (8 * offset)) & 0xff;
|
|
|
|
return rval;
|
|
}
|
|
|
|
inline u_int16_t
|
|
__C(CHIP,_io_read_2)(v, ioh, off)
|
|
void *v;
|
|
bus_space_handle_t ioh;
|
|
bus_size_t off;
|
|
{
|
|
register bus_space_handle_t tmpioh;
|
|
register u_int32_t *port, val;
|
|
register u_int16_t rval;
|
|
register int offset;
|
|
|
|
alpha_mb();
|
|
|
|
tmpioh = ioh + off;
|
|
offset = tmpioh & 3;
|
|
port = (u_int32_t *)((tmpioh << 5) | (1 << 3));
|
|
val = *port;
|
|
rval = ((val) >> (8 * offset)) & 0xffff;
|
|
|
|
return rval;
|
|
}
|
|
|
|
inline u_int32_t
|
|
__C(CHIP,_io_read_4)(v, ioh, off)
|
|
void *v;
|
|
bus_space_handle_t ioh;
|
|
bus_size_t off;
|
|
{
|
|
register bus_space_handle_t tmpioh;
|
|
register u_int32_t *port, val;
|
|
register u_int32_t rval;
|
|
register int offset;
|
|
|
|
alpha_mb();
|
|
|
|
tmpioh = ioh + off;
|
|
offset = tmpioh & 3;
|
|
port = (u_int32_t *)((tmpioh << 5) | (3 << 3));
|
|
val = *port;
|
|
#if 0
|
|
rval = ((val) >> (8 * offset)) & 0xffffffff;
|
|
#else
|
|
rval = val;
|
|
#endif
|
|
|
|
return rval;
|
|
}
|
|
|
|
inline u_int64_t
|
|
__C(CHIP,_io_read_8)(v, ioh, off)
|
|
void *v;
|
|
bus_space_handle_t ioh;
|
|
bus_size_t off;
|
|
{
|
|
|
|
/* XXX XXX XXX */
|
|
panic("%s not implemented", __S(__C(CHIP,_io_read_8)));
|
|
}
|
|
|
|
#define CHIP_io_read_multi_N(BYTES,TYPE) \
|
|
void \
|
|
__C(__C(CHIP,_io_read_multi_),BYTES)(v, h, o, a, c) \
|
|
void *v; \
|
|
bus_space_handle_t h; \
|
|
bus_size_t o, c; \
|
|
TYPE *a; \
|
|
{ \
|
|
\
|
|
while (c-- > 0) { \
|
|
__C(CHIP,_io_barrier)(v, h, o, sizeof *a, \
|
|
BUS_BARRIER_READ); \
|
|
*a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \
|
|
} \
|
|
}
|
|
CHIP_io_read_multi_N(1,u_int8_t)
|
|
CHIP_io_read_multi_N(2,u_int16_t)
|
|
CHIP_io_read_multi_N(4,u_int32_t)
|
|
CHIP_io_read_multi_N(8,u_int64_t)
|
|
|
|
#define CHIP_io_read_region_N(BYTES,TYPE) \
|
|
void \
|
|
__C(__C(CHIP,_io_read_region_),BYTES)(v, h, o, a, c) \
|
|
void *v; \
|
|
bus_space_handle_t h; \
|
|
bus_size_t o, c; \
|
|
TYPE *a; \
|
|
{ \
|
|
\
|
|
while (c-- > 0) { \
|
|
*a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \
|
|
o += sizeof *a; \
|
|
} \
|
|
}
|
|
CHIP_io_read_region_N(1,u_int8_t)
|
|
CHIP_io_read_region_N(2,u_int16_t)
|
|
CHIP_io_read_region_N(4,u_int32_t)
|
|
CHIP_io_read_region_N(8,u_int64_t)
|
|
|
|
inline void
|
|
__C(CHIP,_io_write_1)(v, ioh, off, val)
|
|
void *v;
|
|
bus_space_handle_t ioh;
|
|
bus_size_t off;
|
|
u_int8_t val;
|
|
{
|
|
register bus_space_handle_t tmpioh;
|
|
register u_int32_t *port, nval;
|
|
register int offset;
|
|
|
|
tmpioh = ioh + off;
|
|
offset = tmpioh & 3;
|
|
nval = val << (8 * offset);
|
|
port = (u_int32_t *)((tmpioh << 5) | (0 << 3));
|
|
*port = nval;
|
|
alpha_mb();
|
|
}
|
|
|
|
inline void
|
|
__C(CHIP,_io_write_2)(v, ioh, off, val)
|
|
void *v;
|
|
bus_space_handle_t ioh;
|
|
bus_size_t off;
|
|
u_int16_t val;
|
|
{
|
|
register bus_space_handle_t tmpioh;
|
|
register u_int32_t *port, nval;
|
|
register int offset;
|
|
|
|
tmpioh = ioh + off;
|
|
offset = tmpioh & 3;
|
|
nval = val << (8 * offset);
|
|
port = (u_int32_t *)((tmpioh << 5) | (1 << 3));
|
|
*port = nval;
|
|
alpha_mb();
|
|
}
|
|
|
|
inline void
|
|
__C(CHIP,_io_write_4)(v, ioh, off, val)
|
|
void *v;
|
|
bus_space_handle_t ioh;
|
|
bus_size_t off;
|
|
u_int32_t val;
|
|
{
|
|
register bus_space_handle_t tmpioh;
|
|
register u_int32_t *port, nval;
|
|
register int offset;
|
|
|
|
tmpioh = ioh + off;
|
|
offset = tmpioh & 3;
|
|
nval = val /*<< (8 * offset)*/;
|
|
port = (u_int32_t *)((tmpioh << 5) | (3 << 3));
|
|
*port = nval;
|
|
alpha_mb();
|
|
}
|
|
|
|
inline void
|
|
__C(CHIP,_io_write_8)(v, ioh, off, val)
|
|
void *v;
|
|
bus_space_handle_t ioh;
|
|
bus_size_t off;
|
|
u_int64_t val;
|
|
{
|
|
|
|
/* XXX XXX XXX */
|
|
panic("%s not implemented", __S(__C(CHIP,_io_write_8)));
|
|
alpha_mb();
|
|
}
|
|
|
|
#define CHIP_io_write_multi_N(BYTES,TYPE) \
|
|
void \
|
|
__C(__C(CHIP,_io_write_multi_),BYTES)(v, h, o, a, c) \
|
|
void *v; \
|
|
bus_space_handle_t h; \
|
|
bus_size_t o, c; \
|
|
const TYPE *a; \
|
|
{ \
|
|
\
|
|
while (c-- > 0) { \
|
|
__C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \
|
|
__C(CHIP,_io_barrier)(v, h, o, sizeof *a, \
|
|
BUS_BARRIER_WRITE); \
|
|
} \
|
|
}
|
|
CHIP_io_write_multi_N(1,u_int8_t)
|
|
CHIP_io_write_multi_N(2,u_int16_t)
|
|
CHIP_io_write_multi_N(4,u_int32_t)
|
|
CHIP_io_write_multi_N(8,u_int64_t)
|
|
|
|
#define CHIP_io_write_region_N(BYTES,TYPE) \
|
|
void \
|
|
__C(__C(CHIP,_io_write_region_),BYTES)(v, h, o, a, c) \
|
|
void *v; \
|
|
bus_space_handle_t h; \
|
|
bus_size_t o, c; \
|
|
const TYPE *a; \
|
|
{ \
|
|
\
|
|
while (c-- > 0) { \
|
|
__C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \
|
|
o += sizeof *a; \
|
|
} \
|
|
}
|
|
CHIP_io_write_region_N(1,u_int8_t)
|
|
CHIP_io_write_region_N(2,u_int16_t)
|
|
CHIP_io_write_region_N(4,u_int32_t)
|
|
CHIP_io_write_region_N(8,u_int64_t)
|
|
|
|
#define CHIP_io_set_multi_N(BYTES,TYPE) \
|
|
void \
|
|
__C(__C(CHIP,_io_set_multi_),BYTES)(v, h, o, val, c) \
|
|
void *v; \
|
|
bus_space_handle_t h; \
|
|
bus_size_t o, c; \
|
|
TYPE val; \
|
|
{ \
|
|
\
|
|
while (c-- > 0) { \
|
|
__C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \
|
|
__C(CHIP,_io_barrier)(v, h, o, sizeof val, \
|
|
BUS_BARRIER_WRITE); \
|
|
} \
|
|
}
|
|
CHIP_io_set_multi_N(1,u_int8_t)
|
|
CHIP_io_set_multi_N(2,u_int16_t)
|
|
CHIP_io_set_multi_N(4,u_int32_t)
|
|
CHIP_io_set_multi_N(8,u_int64_t)
|
|
|
|
#define CHIP_io_set_region_N(BYTES,TYPE) \
|
|
void \
|
|
__C(__C(CHIP,_io_set_region_),BYTES)(v, h, o, val, c) \
|
|
void *v; \
|
|
bus_space_handle_t h; \
|
|
bus_size_t o, c; \
|
|
TYPE val; \
|
|
{ \
|
|
\
|
|
while (c-- > 0) { \
|
|
__C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \
|
|
o += sizeof val; \
|
|
} \
|
|
}
|
|
CHIP_io_set_region_N(1,u_int8_t)
|
|
CHIP_io_set_region_N(2,u_int16_t)
|
|
CHIP_io_set_region_N(4,u_int32_t)
|
|
CHIP_io_set_region_N(8,u_int64_t)
|
|
|
|
#define CHIP_io_copy_N(BYTES) \
|
|
void \
|
|
__C(__C(CHIP,_io_copy_),BYTES)(v, h1, o1, h2, o2, c) \
|
|
void *v; \
|
|
bus_space_handle_t h1, h2; \
|
|
bus_size_t o1, o2, c; \
|
|
{ \
|
|
bus_size_t i, o; \
|
|
\
|
|
for (i = 0, o = 0; i < c; i++, o += BYTES) \
|
|
__C(__C(CHIP,_io_write_),BYTES)(v, h2, o2 + o, \
|
|
__C(__C(CHIP,_io_read_),BYTES)(v, h1, o1 + o)); \
|
|
}
|
|
CHIP_io_copy_N(1)
|
|
CHIP_io_copy_N(2)
|
|
CHIP_io_copy_N(4)
|
|
CHIP_io_copy_N(8)
|