407 lines
12 KiB
C
407 lines
12 KiB
C
/* $NetBSD: mem.c,v 1.16 2008/06/13 09:41:44 cegger Exp $ */
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/* $OpenBSD: mem.c,v 1.5 2001/05/05 20:56:36 art Exp $ */
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/*
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* Copyright (c) 1998,1999 Michael Shalayeff
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Michael Shalayeff.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF MIND,
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1991,1992,1994, The University of Utah and
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* the Computer Systems Laboratory (CSL). All rights reserved.
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*
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* Subject to your agreements with CMU,
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* permission to use, copy, modify and distribute this software and its
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* documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* THE UNIVERSITY OF UTAH AND CSL ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS
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* IS" CONDITION. THE UNIVERSITY OF UTAH AND CSL DISCLAIM ANY LIABILITY OF
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* ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* CSL requests users of this software to return to csl-dist@cs.utah.edu any
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* improvements that they make and grant CSL redistribution rights.
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*
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* Utah $Hdr: mem.c 1.9 94/12/16$
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*/
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/*
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* Mach Operating System
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* Copyright (c) 1992 Carnegie Mellon University
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* All Rights Reserved.
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*
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* Permission to use, copy, modify and distribute this software and its
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* documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
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* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie Mellon
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* the rights to redistribute these changes.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: mem.c,v 1.16 2008/06/13 09:41:44 cegger Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/buf.h>
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#include <sys/conf.h>
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#include <sys/malloc.h>
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#include <sys/proc.h>
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#include <sys/uio.h>
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#include <sys/types.h>
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#include <sys/device.h>
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#include <sys/errno.h>
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#include <sys/ioctl.h>
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#include <sys/file.h>
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#include <sys/bus.h>
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#include <sys/mutex.h>
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#include <uvm/uvm.h>
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#include <machine/iomod.h>
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#include <machine/autoconf.h>
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#include <machine/pmap.h>
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#include <hp700/hp700/machdep.h>
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#include <hp700/dev/cpudevs.h>
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#include <hp700/dev/viper.h>
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/* registers on the PCXL2 MIOC */
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struct l2_mioc {
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uint32_t pad[0x20]; /* 0x000 */
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uint32_t mioc_control; /* 0x080 MIOC control bits */
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uint32_t mioc_status; /* 0x084 MIOC status bits */
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uint32_t pad1[6]; /* 0x088 */
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uint32_t sltcv; /* 0x0a0 L2 cache control */
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#define SLTCV_AVWL 0x00002000 /* extra cycle for addr valid write low */
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#define SLTCV_UP4COUT 0x00001000 /* update cache on CPU castouts */
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#define SLTCV_EDCEN 0x08000000 /* enable error correction */
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#define SLTCV_EDTAG 0x10000000 /* enable diagtag */
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#define SLTCV_CHKTP 0x20000000 /* enable parity checking */
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#define SLTCV_LOWPWR 0x40000000 /* low power mode */
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#define SLTCV_ENABLE 0x80000000 /* enable L2 cache */
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#define SLTCV_BITS "\020\15avwl\16up4cout\24edcen\25edtag\26chktp\27lowpwr\30l2ena"
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uint32_t tagmask; /* 0x0a4 L2 cache tag mask */
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uint32_t diagtag; /* 0x0a8 L2 invalidates tag */
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uint32_t sltestat; /* 0x0ac L2 last logged tag read */
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uint32_t slteadd; /* 0x0b0 L2 pa of -- " -- */
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uint32_t pad2[3]; /* 0x0b4 */
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uint32_t mtcv; /* 0x0c0 MIOC timings */
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uint32_t ref; /* 0x0cc MIOC refresh timings */
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uint32_t pad3[4]; /* 0x0d0 */
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uint32_t mderradd; /* 0x0e0 addr of most evil mem error */
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uint32_t pad4; /* 0x0e4 */
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uint32_t dmaerr; /* 0x0e8 addr of most evil dma error */
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uint32_t dioerr; /* 0x0ec addr of most evil dio error */
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uint32_t gsc_timeout; /* 0x0f0 1-compl of GSC timeout delay */
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uint32_t hidmamem; /* 0x0f4 amount of phys mem installed */
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uint32_t pad5[2]; /* 0x0f8 */
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uint32_t memcomp[16]; /* 0x100 memory address comparators */
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uint32_t memmask[16]; /* 0x140 masks for -- " -- */
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uint32_t memtest; /* 0x180 test address decoding */
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uint32_t pad6[0xf]; /* 0x184 */
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uint32_t outchk; /* 0x1c0 address decoding output */
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uint32_t pad7[0x168]; /* 0x200 */
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uint32_t gsc15x_config; /* 0x7a0 writev enable */
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};
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struct mem_softc {
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struct device sc_dev;
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volatile struct vi_trs *sc_vp;
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volatile struct l2_mioc *sc_l2;
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};
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int memmatch(struct device *, struct cfdata *, void *);
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void memattach(struct device *, struct device *, void *);
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CFATTACH_DECL(mem, sizeof(struct mem_softc),
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memmatch, memattach, NULL, NULL);
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extern struct cfdriver mem_cd;
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dev_type_read(mmrw);
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dev_type_ioctl(mmioctl);
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dev_type_mmap(mmmmap);
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const struct cdevsw mem_cdevsw = {
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nullopen, nullclose, mmrw, mmrw, mmioctl,
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nostop, notty, nopoll, mmmmap,
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};
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static void *zeropage;
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/* A lock for the vmmap. */
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kmutex_t vmmap_lock;
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int
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memmatch(struct device *parent, struct cfdata *cf, void *aux)
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{
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struct confargs *ca = aux;
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if (ca->ca_type.iodc_type != HPPA_TYPE_MEMORY ||
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ca->ca_type.iodc_sv_model != HPPA_MEMORY_PDEP)
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return 0;
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return 1;
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}
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void
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memattach(struct device *parent, struct device *self, void *aux)
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{
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struct pdc_iodc_minit pdc_minit PDC_ALIGNMENT;
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struct confargs *ca = aux;
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struct mem_softc *sc = (struct mem_softc *)self;
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int s, err, pagezero_cookie;
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char bits[128];
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printf (":");
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pagezero_cookie = hp700_pagezero_map();
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/* XXX check if we are dealing w/ Viper */
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if (ca->ca_hpa == (hppa_hpa_t)VIPER_HPA) {
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sc->sc_vp = (struct vi_trs *)
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&((struct iomod *)ca->ca_hpa)->priv_trs;
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/* XXX other values seem to blow it up */
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if (sc->sc_vp->vi_status.hw_rev == 0) {
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bitmask_snprintf(VI_CTRL, VIPER_BITS, bits,
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sizeof(bits));
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printf (" viper rev %x, ctrl %s",
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sc->sc_vp->vi_status.hw_rev,
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bits);
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s = splhigh();
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VI_CTRL |= VI_CTRL_ANYDEN;
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((struct vi_ctrl *)&VI_CTRL)->core_den = 0;
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((struct vi_ctrl *)&VI_CTRL)->sgc0_den = 0;
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((struct vi_ctrl *)&VI_CTRL)->sgc1_den = 0;
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((struct vi_ctrl *)&VI_CTRL)->core_prf = 1;
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sc->sc_vp->vi_control = VI_CTRL;
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splx(s);
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#ifdef DEBUG
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bitmask_snprintf(VI_CTRL, VIPER_BITS, bits,
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sizeof(bits));
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printf (" >> %s", bits);
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#endif
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} else
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sc->sc_vp = NULL;
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} else
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sc->sc_vp = NULL;
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if ((err = pdc_call((iodcio_t)pdc, 0, PDC_IODC, PDC_IODC_NINIT,
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&pdc_minit, ca->ca_hpa, PAGE0->imm_spa_size)) < 0)
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pdc_minit.max_spa = PAGE0->imm_max_mem;
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hp700_pagezero_unmap(pagezero_cookie);
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printf (" size %d", pdc_minit.max_spa / (1024*1024));
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if (pdc_minit.max_spa % (1024*1024))
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printf (".%d", pdc_minit.max_spa % (1024*1024));
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printf ("MB");
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/* L2 cache controller is a part of the memory controller on PCXL2 */
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if (HPPA_PA_SPEC_MAJOR(hppa_cpu_info->hppa_cpu_info_pa_spec) == 1 &&
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HPPA_PA_SPEC_MINOR(hppa_cpu_info->hppa_cpu_info_pa_spec) == 1 &&
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HPPA_PA_SPEC_LETTER(hppa_cpu_info->hppa_cpu_info_pa_spec) == 'e') {
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sc->sc_l2 = (struct l2_mioc *)ca->ca_hpa;
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#ifdef DEBUG
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bitmask_snprintf(sc->sc_l2->sltcv, SLTCV_BITS, bits,
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sizeof(bits));
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printf(", sltcv %s", bits);
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#endif
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/* sc->sc_l2->sltcv |= SLTCV_UP4COUT; */
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if (sc->sc_l2->sltcv & SLTCV_ENABLE) {
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uint32_t tagmask = sc->sc_l2->tagmask >> 20;
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printf(", %dMB L2 cache", tagmask + 1);
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}
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}
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printf("\n");
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}
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void
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viper_setintrwnd(uint32_t mask)
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{
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struct mem_softc *sc;
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sc = device_lookup_private(&mem_cd,0);
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if (sc->sc_vp)
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sc->sc_vp->vi_intrwd;
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}
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void
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viper_eisa_en(void)
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{
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struct mem_softc *sc;
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int pagezero_cookie;
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sc = device_lookup_private(&mem_cd, 0);
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pagezero_cookie = hp700_pagezero_map();
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if (sc->sc_vp)
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((struct vi_ctrl *)&VI_CTRL)->eisa_den = 0;
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hp700_pagezero_unmap(pagezero_cookie);
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}
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int
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mmrw(dev_t dev, struct uio *uio, int flags)
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{
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struct iovec *iov;
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vaddr_t v, o;
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vm_prot_t prot;
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u_int c;
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int error = 0;
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int rw;
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while (uio->uio_resid > 0 && error == 0) {
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iov = uio->uio_iov;
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if (iov->iov_len == 0) {
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uio->uio_iov++;
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uio->uio_iovcnt--;
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if (uio->uio_iovcnt < 0)
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panic("mmrw");
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continue;
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}
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switch (minor(dev)) {
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case DEV_MEM: /* /dev/mem */
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/* If the address isn't in RAM, bail. */
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v = uio->uio_offset;
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if (btoc(v) > totalphysmem) {
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error = EFAULT;
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/* this will break us out of the loop */
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continue;
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}
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/*
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* If the address is inside our large
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* directly-mapped kernel BTLB entries,
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* use kmem instead.
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*/
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if (v < virtual_start) {
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goto use_kmem;
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}
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mutex_enter(&vmmap_lock);
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/* Temporarily map the memory at vmmap. */
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prot = uio->uio_rw == UIO_READ ? VM_PROT_READ :
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VM_PROT_WRITE;
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pmap_enter(pmap_kernel(), (vaddr_t)vmmap,
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trunc_page(v), prot, prot|PMAP_WIRED);
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pmap_update(pmap_kernel());
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o = v & PGOFSET;
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c = min(uio->uio_resid, (int)(PAGE_SIZE - o));
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error = uiomove((char *)vmmap + o, c, uio);
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pmap_remove(pmap_kernel(), (vaddr_t)vmmap,
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(vaddr_t)vmmap + PAGE_SIZE);
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pmap_update(pmap_kernel());
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mutex_exit(&vmmap_lock);
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break;
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case DEV_KMEM: /* /dev/kmem */
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v = uio->uio_offset;
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use_kmem:
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o = v & PGOFSET;
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c = min(uio->uio_resid, (int)(PAGE_SIZE - o));
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rw = (uio->uio_rw == UIO_READ) ? B_READ : B_WRITE;
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if (!uvm_kernacc((void *)v, c, rw)) {
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error = EFAULT;
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/* this will break us out of the loop */
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continue;
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}
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error = uiomove((void *)v, c, uio);
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break;
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case DEV_NULL: /* /dev/null */
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if (uio->uio_rw == UIO_WRITE)
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uio->uio_resid = 0;
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return (0);
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case DEV_ZERO: /* /dev/zero */
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/* Write to /dev/zero is ignored. */
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if (uio->uio_rw == UIO_WRITE) {
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uio->uio_resid = 0;
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return (0);
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}
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/*
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* On the first call, allocate and zero a page
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* of memory for use with /dev/zero.
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*/
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if (zeropage == NULL) {
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zeropage = (void *)
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malloc(PAGE_SIZE, M_TEMP, M_WAITOK);
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memset(zeropage, 0, PAGE_SIZE);
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}
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c = min(iov->iov_len, PAGE_SIZE);
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error = uiomove(zeropage, c, uio);
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break;
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default:
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return (ENXIO);
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}
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}
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return (error);
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}
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paddr_t
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mmmmap(dev_t dev, off_t off, int prot)
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{
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if (minor(dev) != 0)
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return (-1);
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/*
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* Allow access only in RAM.
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*/
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#if 0
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if (off < ctob(firstusablepage) ||
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off >= ctob(lastusablepage + 1))
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return (-1);
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#endif
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return (btop(off));
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}
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