136 lines
3.2 KiB
ArmAsm
136 lines
3.2 KiB
ArmAsm
/* $NetBSD: prom_swpal.S,v 1.2 1997/04/06 08:41:01 cgd Exp $ */
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/*
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* Copyright (c) 1994, 1995 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Keith Bostic
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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#include "../../include/asm.h"
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#include "../../include/prom.h"
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#include "../../include/rpb.h"
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/* Offsets from base of HWRPB. */
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#define RPB_SELFREF 0x00
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#define RPB_SLOTSIZE 0x98
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#define RPB_PERCPU_OFF 0xA0
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/* Offsets in a boot PCB. */
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#define PCB_KSP 0x00
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#define PCB_PTBR 0x10
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#define PCB_ASN 0x1c
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#define PCB_FEN 0x28
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/* Pal values. */
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#define PAL_RESERVED 0 /* Reserved to Digital. */
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#define PAL_VMS 1 /* VMS */
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#define PAL_OSF 2 /* OSF */
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/*
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* PAL code switch routine.
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*/
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#define D_RA (7*8)
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#define D_S0 (8*8)
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#define D_S1 (9*8)
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#define D_S2 (10*8)
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#define D_S3 (11*8)
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#define D_S4 (12*8)
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#define D_S5 (13*8)
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#define PALSW_FRAME_SIZE (14*8)
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#define PALSW_REGS IM_RA|IM_S0|IM_S1|IM_S2|IM_S3|IM_S4|IM_S5
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.comm ptbr_save,8
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.text
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.align 4
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NESTED(switch_palcode, 0, PALSW_FRAME_SIZE, ra, PALSW_REGS, 0)
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LDGP(pv)
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/* ldgp gp, 0(pv)*/
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lda sp, -PALSW_FRAME_SIZE(sp)
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stq ra, D_RA(sp)
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stq s0, D_S0(sp)
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stq s1, D_S1(sp)
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stq s2, D_S2(sp)
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stq s3, D_S3(sp)
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stq s4, D_S4(sp)
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stq s5, D_S5(sp)
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stq pv, 0(sp)
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stq gp, 8(sp)
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ldiq s0, HWRPB_ADDR /* s0 HWRPB_ADDR */
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ldq s1, RPB_SLOTSIZE(s0)
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call_pal PAL_VMS_mfpr_whami
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mulq s1, v0, s1 /* s1 per_cpu offset from base */
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ldq s2, RPB_PERCPU_OFF(s0)
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addq s0, s2, s2
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addq s2, s1, s2 /* s2 PCB (virtual) */
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call_pal PAL_VMS_mfpr_ptbr
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stq v0, PCB_PTBR(s2)
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stq v0, ptbr_save /* save PTBR for the kernel */
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stl zero, PCB_ASN(s2)
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stq zero, PCB_FEN(s2)
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stq sp, PCB_KSP(s2)
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ldq t0, RPB_SELFREF(s0) /* HWRBP base (physical) */
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ldq t1, RPB_PERCPU_OFF(s0)
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addq t0, t1, t0
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addq t0, s1, t0 /* PCB base (phys) */
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stq t0, 16(sp)
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call_pal PAL_VMS_mfpr_vptb
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mov v0, a3
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ldiq a0, PAL_OSF
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lda a1, contin
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ldq a2, 16(sp)
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call_pal PAL_swppal /* a0, a1, a2, a3 */
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contin: ldq pv, 0(sp)
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ldq gp, 8(sp)
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ldq ra, D_RA(sp)
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ldq s0, D_S0(sp)
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ldq s1, D_S1(sp)
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ldq s2, D_S2(sp)
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ldq s3, D_S3(sp)
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ldq s4, D_S4(sp)
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ldq s5, D_S5(sp)
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lda sp, PALSW_FRAME_SIZE(sp)
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RET
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END(switch_palcode)
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#undef D_RA
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#undef D_S0
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#undef D_S1
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#undef D_S2
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#undef D_S3
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#undef D_S4
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#undef D_S5
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#undef PALSW_FRAME_SIZE
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#undef PALSW_REGS
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