347 lines
9.1 KiB
C
347 lines
9.1 KiB
C
/* $NetBSD: sio_pic.c,v 1.19 1997/09/02 13:19:53 thorpej Exp $ */
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/*
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* Copyright (c) 1995, 1996 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: sio_pic.c,v 1.19 1997/09/02 13:19:53 thorpej Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <sys/syslog.h>
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#include <machine/intr.h>
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#include <machine/bus.h>
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#include <dev/isa/isareg.h>
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#include <dev/isa/isavar.h>
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#include <alpha/pci/siovar.h>
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#ifndef EVCNT_COUNTERS
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#include <machine/intrcnt.h>
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#endif
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#include "sio.h"
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/*
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* To add to the long history of wonderful PROM console traits,
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* AlphaStation PROMs don't reset themselves completely on boot!
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* Therefore, if an interrupt was turned on when the kernel was
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* started, we're not going to EVER turn it off... I don't know
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* what will happen if new interrupts (that the PROM console doesn't
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* want) are turned on. I'll burn that bridge when I come to it.
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*/
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#define BROKEN_PROM_CONSOLE
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/*
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* Private functions and variables.
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*/
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bus_space_tag_t sio_iot;
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bus_space_handle_t sio_ioh_icu1, sio_ioh_icu2, sio_ioh_elcr;
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#define ICU_LEN 16 /* number of ISA IRQs */
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static struct alpha_shared_intr *sio_intr;
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#ifdef EVCNT_COUNTERS
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struct evcnt sio_intr_evcnt;
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#endif
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#ifndef STRAY_MAX
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#ifdef BROKEN_PROM_CONSOLE
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/*
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* If prom console is broken, because initial interrupt settings
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* must be kept, there's no way to escape stray interrupts.
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*/
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#define STRAY_MAX 0
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#else
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#define STRAY_MAX 5
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#endif
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#endif
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#ifdef BROKEN_PROM_CONSOLE
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/*
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* If prom console is broken, must remember the initial interrupt
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* settings and enforce them. WHEE!
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*/
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u_int8_t initial_ocw1[2];
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u_int8_t initial_elcr[2];
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#define INITIALLY_ENABLED(irq) \
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((initial_ocw1[(irq) / 8] & (1 << ((irq) % 8))) == 0)
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#define INITIALLY_LEVEL_TRIGGERED(irq) \
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((initial_elcr[(irq) / 8] & (1 << ((irq) % 8))) != 0)
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#else
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#define INITIALLY_ENABLED(irq) ((irq) == 2 ? 1 : 0)
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#define INITIALLY_LEVEL_TRIGGERED(irq) 0
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#endif
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void sio_setirqstat __P((int, int, int));
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void
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sio_setirqstat(irq, enabled, type)
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int irq, enabled;
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int type;
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{
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u_int8_t ocw1[2], elcr[2];
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int icu, bit;
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#if 0
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printf("sio_setirqstat: irq %d: %s, %s\n", irq,
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enabled ? "enabled" : "disabled", isa_intr_typename(type));
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#endif
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icu = irq / 8;
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bit = irq % 8;
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ocw1[0] = bus_space_read_1(sio_iot, sio_ioh_icu1, 1);
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ocw1[1] = bus_space_read_1(sio_iot, sio_ioh_icu2, 1);
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elcr[0] = bus_space_read_1(sio_iot, sio_ioh_elcr, 0); /* XXX */
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elcr[1] = bus_space_read_1(sio_iot, sio_ioh_elcr, 1); /* XXX */
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/*
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* interrupt enable: set bit to mask (disable) interrupt.
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*/
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if (enabled)
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ocw1[icu] &= ~(1 << bit);
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else
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ocw1[icu] |= 1 << bit;
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/*
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* interrupt type select: set bit to get level-triggered.
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*/
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if (type == IST_LEVEL)
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elcr[icu] |= 1 << bit;
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else
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elcr[icu] &= ~(1 << bit);
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#ifdef not_here
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/* see the init function... */
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ocw1[0] &= ~0x04; /* always enable IRQ2 on first PIC */
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elcr[0] &= ~0x07; /* IRQ[0-2] must be edge-triggered */
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elcr[1] &= ~0x21; /* IRQ[13,8] must be edge-triggered */
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#endif
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#ifdef BROKEN_PROM_CONSOLE
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/*
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* make sure that the initially clear bits (unmasked interrupts)
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* are never set, and that the initially-level-triggered
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* intrrupts always remain level-triggered, to keep the prom happy.
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*/
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if ((ocw1[0] & ~initial_ocw1[0]) != 0 ||
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(ocw1[1] & ~initial_ocw1[1]) != 0 ||
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(elcr[0] & initial_elcr[0]) != initial_elcr[0] ||
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(elcr[1] & initial_elcr[1]) != initial_elcr[1]) {
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printf("sio_sis: initial: ocw = (%2x,%2x), elcr = (%2x,%2x)\n",
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initial_ocw1[0], initial_ocw1[1],
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initial_elcr[0], initial_elcr[1]);
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printf(" current: ocw = (%2x,%2x), elcr = (%2x,%2x)\n",
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ocw1[0], ocw1[1], elcr[0], elcr[1]);
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panic("sio_setirqstat: hosed");
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}
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#endif
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bus_space_write_1(sio_iot, sio_ioh_icu1, 1, ocw1[0]);
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bus_space_write_1(sio_iot, sio_ioh_icu2, 1, ocw1[1]);
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bus_space_write_1(sio_iot, sio_ioh_elcr, 0, elcr[0]); /* XXX */
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bus_space_write_1(sio_iot, sio_ioh_elcr, 1, elcr[1]); /* XXX */
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}
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void
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sio_intr_setup(iot)
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bus_space_tag_t iot;
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{
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int i;
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sio_iot = iot;
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if (bus_space_map(sio_iot, IO_ICU1, IO_ICUSIZE, 0, &sio_ioh_icu1) ||
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bus_space_map(sio_iot, IO_ICU2, IO_ICUSIZE, 0, &sio_ioh_icu2) ||
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bus_space_map(sio_iot, 0x4d0, 2, 0, &sio_ioh_elcr))
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panic("sio_intr_setup: can't map I/O ports");
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#ifdef BROKEN_PROM_CONSOLE
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/*
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* Remember the initial values, because the prom is stupid.
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*/
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initial_ocw1[0] = bus_space_read_1(sio_iot, sio_ioh_icu1, 1);
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initial_ocw1[1] = bus_space_read_1(sio_iot, sio_ioh_icu2, 1);
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initial_elcr[0] = bus_space_read_1(sio_iot, sio_ioh_elcr, 0); /* XXX */
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initial_elcr[1] = bus_space_read_1(sio_iot, sio_ioh_elcr, 1); /* XXX */
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#if 0
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printf("initial_ocw1[0] = 0x%x\n", initial_ocw1[0]);
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printf("initial_ocw1[1] = 0x%x\n", initial_ocw1[1]);
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printf("initial_elcr[0] = 0x%x\n", initial_elcr[0]);
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printf("initial_elcr[1] = 0x%x\n", initial_elcr[1]);
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#endif
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#endif
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sio_intr = alpha_shared_intr_alloc(ICU_LEN);
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/*
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* set up initial values for interrupt enables.
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*/
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for (i = 0; i < ICU_LEN; i++) {
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alpha_shared_intr_set_maxstrays(sio_intr, i, STRAY_MAX);
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switch (i) {
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case 0:
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case 1:
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case 8:
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case 13:
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/*
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* IRQs 0, 1, 8, and 13 must always be
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* edge-triggered.
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*/
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if (INITIALLY_LEVEL_TRIGGERED(i))
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printf("sio_intr_setup: %d LT!\n", i);
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sio_setirqstat(i, INITIALLY_ENABLED(i), IST_EDGE);
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alpha_shared_intr_set_dfltsharetype(sio_intr, i,
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IST_EDGE);
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break;
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case 2:
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/*
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* IRQ 2 must be edge-triggered, and should be
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* enabled (otherwise IRQs 8-15 are ignored).
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*/
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if (INITIALLY_LEVEL_TRIGGERED(i))
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printf("sio_intr_setup: %d LT!\n", i);
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if (!INITIALLY_ENABLED(i))
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printf("sio_intr_setup: %d not enabled!\n", i);
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sio_setirqstat(i, 1, IST_EDGE);
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alpha_shared_intr_set_dfltsharetype(sio_intr, i,
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IST_UNUSABLE);
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break;
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default:
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/*
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* Otherwise, disable the IRQ and set its
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* type to (effectively) "unknown."
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*/
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sio_setirqstat(i, INITIALLY_ENABLED(i),
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INITIALLY_LEVEL_TRIGGERED(i) ? IST_LEVEL :
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IST_NONE);
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alpha_shared_intr_set_dfltsharetype(sio_intr, i,
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INITIALLY_LEVEL_TRIGGERED(i) ? IST_LEVEL :
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IST_NONE);
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break;
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}
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}
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}
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const char *
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sio_intr_string(v, irq)
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void *v;
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int irq;
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{
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static char irqstr[12]; /* 8 + 2 + NULL + sanity */
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if (irq == 0 || irq >= ICU_LEN || irq == 2)
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panic("sio_intr_string: bogus isa irq 0x%x\n", irq);
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sprintf(irqstr, "isa irq %d", irq);
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return (irqstr);
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}
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void *
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sio_intr_establish(v, irq, type, level, fn, arg)
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void *v, *arg;
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int irq;
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int type;
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int level;
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int (*fn)(void *);
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{
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void *cookie;
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if (irq > ICU_LEN || type == IST_NONE)
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panic("sio_intr_establish: bogus irq or type");
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cookie = alpha_shared_intr_establish(sio_intr, irq, type, level, fn,
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arg, "isa irq");
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if (cookie)
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sio_setirqstat(irq, alpha_shared_intr_isactive(sio_intr, irq),
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alpha_shared_intr_get_sharetype(sio_intr, irq));
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return (cookie);
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}
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void
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sio_intr_disestablish(v, cookie)
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void *v;
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void *cookie;
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{
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printf("sio_intr_disestablish(%p)\n", cookie);
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/* XXX */
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/* XXX NEVER ALLOW AN INITIALLY-ENABLED INTERRUPT TO BE DISABLED */
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/* XXX NEVER ALLOW AN INITIALLY-LT INTERRUPT TO BECOME UNTYPED */
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}
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void
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sio_iointr(framep, vec)
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void *framep;
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unsigned long vec;
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{
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int irq;
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irq = (vec - 0x800) >> 4;
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#ifdef DIAGNOSTIC
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if (irq > ICU_LEN || irq < 0)
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panic("sio_iointr: irq out of range (%d)", irq);
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#endif
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#ifdef EVCNT_COUNTERS
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sio_intr_evcnt.ev_count++;
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#else
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#ifdef DEBUG
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if (ICU_LEN != INTRCNT_ISA_IRQ_LEN)
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panic("sio interrupt counter sizes inconsistent");
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#endif
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intrcnt[INTRCNT_ISA_IRQ + irq]++;
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#endif
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if (!alpha_shared_intr_dispatch(sio_intr, irq))
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alpha_shared_intr_stray(sio_intr, irq, "isa irq");
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/*
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* Some versions of the machines which use the SIO
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* (or is it some PALcode revisions on those machines?)
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* require the non-specific EOI to be fed to the PIC(s)
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* by the interrupt handler.
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*/
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if (irq > 7)
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bus_space_write_1(sio_iot,
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sio_ioh_icu2, 0, 0x20 | (irq & 0x07)); /* XXX */
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bus_space_write_1(sio_iot,
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sio_ioh_icu1, 0, 0x20 | (irq > 7 ? 2 : irq)); /* XXX */
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}
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