371 lines
9.1 KiB
C
371 lines
9.1 KiB
C
/* $NetBSD: tegra_machdep.c,v 1.5 2015/04/26 17:40:59 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: tegra_machdep.c,v 1.5 2015/04/26 17:40:59 jmcneill Exp $");
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#include "opt_tegra.h"
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#include "opt_machdep.h"
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#include "opt_ddb.h"
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#include "opt_md.h"
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#include "opt_arm_debug.h"
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#include "opt_multiprocessor.h"
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#include "com.h"
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#include "ukbd.h"
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#include "genfb.h"
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#include "ether.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/atomic.h>
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#include <sys/cpu.h>
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#include <sys/device.h>
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#include <sys/exec.h>
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#include <sys/kernel.h>
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#include <sys/ksyms.h>
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#include <sys/msgbuf.h>
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#include <sys/proc.h>
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#include <sys/reboot.h>
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#include <sys/termios.h>
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#include <sys/gpio.h>
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#include <uvm/uvm_extern.h>
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#include <sys/conf.h>
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#include <dev/cons.h>
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#include <dev/md.h>
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#include <machine/db_machdep.h>
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#include <ddb/db_sym.h>
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#include <ddb/db_extern.h>
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#include <machine/bootconfig.h>
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#include <arm/armreg.h>
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#include <arm/undefined.h>
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#include <arm/arm32/machdep.h>
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#include <arm/mainbus/mainbus.h>
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#include <arm/nvidia/tegra_reg.h>
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#include <arm/nvidia/tegra_var.h>
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#include <arm/cortex/gtmr_var.h>
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#include <evbarm/include/autoconf.h>
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#include <evbarm/tegra/platform.h>
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#include <dev/ic/ns16550reg.h>
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#include <dev/ic/comreg.h>
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#include <dev/ic/comvar.h>
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#include <dev/usb/ukbdvar.h>
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#include <net/if_ether.h>
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#ifndef TEGRA_MAX_BOOT_STRING
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#define TEGRA_MAX_BOOT_STRING 1024
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#endif
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BootConfig bootconfig;
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static char bootargs[TEGRA_MAX_BOOT_STRING];
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char *boot_args = NULL;
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u_int uboot_args[4] = { 0 }; /* filled in by tegra_start.S (not in bss) */
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extern char KERNEL_BASE_phys[];
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#define KERNEL_BASE_PHYS ((paddr_t)KERNEL_BASE_phys)
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static void tegra_device_register(device_t, void *);
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bs_protos(bs_notimpl);
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#define _A(a) ((a) & ~L1_S_OFFSET)
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#define _S(s) (((s) + L1_S_SIZE - 1) & ~(L1_S_SIZE-1))
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static const struct pmap_devmap devmap[] = {
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{
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.pd_va = _A(TEGRA_HOST1X_VBASE),
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.pd_pa = _A(TEGRA_HOST1X_BASE),
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.pd_size = _S(TEGRA_HOST1X_SIZE),
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.pd_prot = VM_PROT_READ|VM_PROT_WRITE,
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.pd_cache = PTE_NOCACHE
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},
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{
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.pd_va = _A(TEGRA_APB_VBASE),
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.pd_pa = _A(TEGRA_APB_BASE),
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.pd_size = _S(TEGRA_APB_SIZE),
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.pd_prot = VM_PROT_READ|VM_PROT_WRITE,
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.pd_cache = PTE_NOCACHE
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},
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{
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.pd_va = _A(TEGRA_AHB_A2_VBASE),
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.pd_pa = _A(TEGRA_AHB_A2_BASE),
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.pd_size = _S(TEGRA_AHB_A2_SIZE),
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.pd_prot = VM_PROT_READ|VM_PROT_WRITE,
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.pd_cache = PTE_NOCACHE
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},
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{0}
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};
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#undef _A
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#undef _S
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#ifdef PMAP_NEED_ALLOC_POOLPAGE
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static struct boot_physmem bp_highgig = {
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.bp_start = TEGRA_EXTMEM_BASE / NBPG,
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.bp_pages = (KERNEL_VM_BASE - KERNEL_BASE) / NBPG,
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.bp_freelist = VM_FREELIST_ISADMA,
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.bp_flags = 0
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};
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#endif
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#ifdef VERBOSE_INIT_ARM
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static void
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tegra_putchar(char c)
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{
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volatile uint32_t *uartaddr = (volatile uint32_t *)CONSADDR_VA;
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int timo = 150000;
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while ((uartaddr[com_lsr] & LSR_TXRDY) == 0) {
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if (--timo == 0)
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break;
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}
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uartaddr[com_data] = c;
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while ((uartaddr[com_lsr] & LSR_TXRDY) == 0) {
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if (--timo == 0)
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break;
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}
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}
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static void
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tegra_putstr(const char *s)
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{
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for (const char *p = s; *p; p++) {
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tegra_putchar(*p);
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}
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}
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static void
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tegra_printn(u_int n, int base)
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{
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char *p, buf[(sizeof(u_int) * NBBY / 3) + 1 + 2 /* ALT + SIGN */];
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p = buf;
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do {
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*p++ = hexdigits[n % base];
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} while (n /= base);
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do {
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tegra_putchar(*--p);
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} while (p > buf);
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}
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#define DPRINTF(...) printf(__VA_ARGS__)
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#define DPRINT(x) tegra_putstr(x)
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#define DPRINTN(x,b) tegra_printn((x), (b))
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#else
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#define DPRINTF(...)
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#define DPRINT(x)
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#define DPRINTN(x,b)
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#endif
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/*
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* u_int initarm(...)
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*
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* Initial entry point on startup. This gets called before main() is
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* entered.
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* It should be responsible for setting up everything that must be
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* in place when main is called.
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* This includes
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* Taking a copy of the boot configuration structure.
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* Initialising the physical console so characters can be printed.
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* Setting up page tables for the kernel
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* Relocating the kernel to the bottom of physical memory
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*/
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u_int
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initarm(void *arg)
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{
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psize_t ram_size = 0;
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DPRINT("initarm:");
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DPRINT(" sctlr<0x");
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DPRINTN(armreg_sctlr_read(), 16);
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DPRINT(">");
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DPRINT(" devmap");
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pmap_devmap_register(devmap);
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DPRINT(" bootstrap");
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tegra_bootstrap();
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/* Heads up ... Setup the CPU / MMU / TLB functions. */
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DPRINT(" cpufunc");
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if (set_cpufuncs())
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panic("cpu not recognized!");
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DPRINT(" consinit");
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consinit();
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DPRINTF(" cbar=%#x", armreg_cbar_read());
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DPRINTF(" ok\n");
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DPRINTF("uboot: args %#x, %#x, %#x, %#x\n",
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uboot_args[0], uboot_args[1], uboot_args[2], uboot_args[3]);
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cpu_reset_address = tegra_pmc_reset;
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/* Talk to the user */
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DPRINTF("\nNetBSD/evbarm (tegra) booting ...\n");
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#ifdef BOOT_ARGS
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char mi_bootargs[] = BOOT_ARGS;
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parse_mi_bootargs(mi_bootargs);
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#endif
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DPRINTF("KERNEL_BASE=0x%x, KERNEL_VM_BASE=0x%x, KERNEL_VM_BASE - KERNEL_BASE=0x%x, KERNEL_BASE_VOFFSET=0x%x\n",
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KERNEL_BASE, KERNEL_VM_BASE, KERNEL_VM_BASE - KERNEL_BASE, KERNEL_BASE_VOFFSET);
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ram_size = tegra_mc_memsize();
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#ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS
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const bool mapallmem_p = true;
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#ifndef PMAP_NEED_ALLOC_POOLPAGE
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if (ram_size > KERNEL_VM_BASE - KERNEL_BASE) {
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printf("%s: dropping RAM size from %luMB to %uMB\n",
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__func__, (unsigned long) (ram_size >> 20),
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(KERNEL_VM_BASE - KERNEL_BASE) >> 20);
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ram_size = KERNEL_VM_BASE - KERNEL_BASE;
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}
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#endif
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#else
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const bool mapallmem_p = false;
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#endif
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/*
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* If MEMSIZE specified less than what we really have, limit ourselves
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* to that.
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*/
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#ifdef MEMSIZE
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if (ram_size == 0 || ram_size > (unsigned)MEMSIZE * 1024 * 1024)
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ram_size = (unsigned)MEMSIZE * 1024 * 1024;
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DPRINTF("ram_size = 0x%x\n", (int)ram_size);
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#else
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KASSERTMSG(ram_size > 0, "RAM size unknown and MEMSIZE undefined");
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#endif
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/* Fake bootconfig structure for the benefit of pmap.c. */
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bootconfig.dramblocks = 1;
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bootconfig.dram[0].address = TEGRA_EXTMEM_BASE; /* DDR PHY addr */
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bootconfig.dram[0].pages = ram_size / PAGE_SIZE;
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KASSERT((armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0);
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arm32_bootmem_init(bootconfig.dram[0].address, ram_size,
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KERNEL_BASE_PHYS);
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arm32_kernel_vm_init(KERNEL_VM_BASE, ARM_VECTORS_HIGH, 0, devmap,
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mapallmem_p);
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if (mapallmem_p) {
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if (uboot_args[3] < ram_size) {
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const char * const args = (const char *)
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(uboot_args[3] + KERNEL_BASE_VOFFSET);
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strlcpy(bootargs, args, sizeof(bootargs));
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}
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}
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DPRINTF("bootargs: %s\n", bootargs);
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boot_args = bootargs;
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parse_mi_bootargs(boot_args);
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evbarm_device_register = tegra_device_register;
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#ifdef PMAP_NEED_ALLOC_POOLPAGE
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if (atop(ram_size) > bp_highgig.bp_pages) {
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bp_highgig.bp_start += atop(ram_size) - bp_highgig.bp_pages;
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arm_poolpage_vmfreelist = bp_highgig.bp_freelist;
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return initarm_common(KERNEL_VM_BASE, KERNEL_VM_SIZE,
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&bp_highgig, 1);
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}
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#endif
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return initarm_common(KERNEL_VM_BASE, KERNEL_VM_SIZE, NULL, 0);
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}
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#if NCOM > 0
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#ifndef CONSADDR
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#error Specify the address of the console UART with the CONSADDR option.
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#endif
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#ifndef CONSPEED
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#define CONSPEED 115200
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#endif
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#ifndef CONMODE
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#define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */
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#endif
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#endif
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void
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consinit(void)
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{
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static bool consinit_called = false;
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if (consinit_called)
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return;
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consinit_called = true;
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#if NCOM > 0
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const bus_space_tag_t bst = &armv7_generic_a4x_bs_tag;
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if (comcnattach(bst, CONSADDR, CONSPEED, TEGRA_UART_FREQ,
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COM_TYPE_NORMAL, CONMODE)) {
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panic("Serial console cannot be initialized.");
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}
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#else
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#error only COM console is supported
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#endif
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}
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void
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tegra_device_register(device_t self, void *aux)
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{
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prop_dictionary_t dict = device_properties(self);
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if (device_is_a(self, "armperiph")
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&& device_is_a(device_parent(self), "mainbus")) {
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struct mainbus_attach_args * const mb = aux;
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mb->mb_iot = &armv7_generic_bs_tag;
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return;
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}
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if (device_is_a(self, "armgtmr")) {
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prop_dictionary_set_uint32(dict, "frequency", TEGRA_REF_FREQ);
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return;
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}
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}
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