6242a54566
in a different fashion. Individually, they have the same functionality, but their layout is different. An example of such a chipset is the Promise 203xx. To be able to deal with this, transform the cmd and dma bus_space handles into an array of handles, each seperately created with bus_space_subregion. The code generated by using the extra indirection shouldn't change much, since the extra indirection is negated by having the offset calculation already done in bus_space_subregion. E.g. bus_space_write_4(tag, handle, offset, value) becomes bus_space_write_4(tag, handles[offset], 0, value) Reviewed by Manuel Bouyer. Tested on wdc_isa, wdc_pcmcia, viaide, piixide (i386) and on cmdide (sparc64).
118 lines
4.3 KiB
C
118 lines
4.3 KiB
C
/* $NetBSD: pciidereg.h,v 1.7 2003/11/27 23:02:40 fvdl Exp $ */
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/*
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* Copyright (c) 1998 Christopher G. Demetriou. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Christopher G. Demetriou
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* for the NetBSD Project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* PCI IDE controller register definitions.
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*
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* Author: Christopher G. Demetriou, March 2, 1998.
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*
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* See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and
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* "Programming Interface for Bus Master IDE Controller, Revision 1.0
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* 5/16/94" from the PCI SIG.
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*/
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/*
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* Number of channels per chip. MUST NOT CHANGE (macros in pciide.c and
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* this file depend on its value).
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*/
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#define PCIIDE_NUM_CHANNELS 2
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/*
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* PCI base address register locations (some are per-channel).
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*/
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#define PCIIDE_REG_CMD_BASE(chan) (0x10 + (8 * (chan)))
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#define PCIIDE_REG_CTL_BASE(chan) (0x14 + (8 * (chan)))
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#define PCIIDE_REG_BUS_MASTER_DMA 0x20
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/*
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* Bits in the PCI Programming Interface register (some are per-channel).
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* Bits 6-4 are defined as read-only in PCI 2.1 specification.
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* Microsoft proposed to use these bits for independant channels
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* enable/disable. This feature is enabled based on the value of bit 6.
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*/
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#define PCIIDE_CHANSTATUS_EN 0x40
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#define PCIIDE_CHAN_EN(chan) (0x20 >> (chan))
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#define PCIIDE_INTERFACE_PCI(chan) (0x01 << (2 * (chan)))
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#define PCIIDE_INTERFACE_SETTABLE(chan) (0x02 << (2 * (chan)))
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#define PCIIDE_INTERFACE_BUS_MASTER_DMA 0x80
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/*
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* Compatibility address/IRQ definitions (some are per-channel).
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*/
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#define PCIIDE_COMPAT_CMD_BASE(chan) ((chan) == 0 ? 0x1f0 : 0x170)
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#define PCIIDE_COMPAT_CMD_SIZE 8
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#define PCIIDE_COMPAT_CTL_BASE(chan) ((chan) == 0 ? 0x3f6 : 0x376)
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#define PCIIDE_COMPAT_CTL_SIZE 1
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#define PCIIDE_COMPAT_IRQ(chan) ((chan) == 0 ? 14 : 15)
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#define PCIIDE_CHANNEL_NAME(chan) ((chan) == 0 ? "primary" : "secondary")
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/*
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* definitions for IDE DMA
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* XXX maybe this should go elsewhere
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*/
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/* secondary channel registers offset */
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#define IDEDMA_SCH_OFFSET 0x08
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#define IDEDMA_NREGS 8
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/* Bus master command register */
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#define IDEDMA_CMD 0x00
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#define IDEDMA_CMD_WRITE 0x08
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#define IDEDMA_CMD_START 0x01
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/* Bus master status register */
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#define IDEDMA_CTL 0x02
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#define IDEDMA_CTL_DRV_DMA(d) (0x20 << (d))
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#define IDEDMA_CTL_INTR 0x04
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#define IDEDMA_CTL_ERR 0x02
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#define IDEDMA_CTL_ACT 0x01
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/* Bus master table pointer register */
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#define IDEDMA_TBL 0x04
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#define IDEDMA_TBL_MASK 0xfffffffc
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#define IDEDMA_TBL_ALIGN 0x00010000
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/* bus master table descriptor */
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struct idedma_table {
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u_int32_t base_addr; /* physical base addr of memory region */
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u_int32_t byte_count; /* memory region length */
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#define IDEDMA_BYTE_COUNT_MASK 0x0000FFFF
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#define IDEDMA_BYTE_COUNT_EOT 0x80000000
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};
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#define IDEDMA_BYTE_COUNT_MAX 0x00010000 /* Max I/O per table */
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#define IDEDMA_BYTE_COUNT_ALIGN 0x00010000
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/* Number of idedma table needed */
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#define NIDEDMA_TABLES (MAXPHYS/PAGE_SIZE + 1)
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