622 lines
19 KiB
C
622 lines
19 KiB
C
/* $NetBSD: cmdide.c,v 1.17 2004/08/21 00:28:34 thorpej Exp $ */
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/*
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* Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Manuel Bouyer.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pciidereg.h>
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#include <dev/pci/pciidevar.h>
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#include <dev/pci/pciide_cmd_reg.h>
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static int cmdide_match(struct device *, struct cfdata *, void *);
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static void cmdide_attach(struct device *, struct device *, void *);
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CFATTACH_DECL(cmdide, sizeof(struct pciide_softc),
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cmdide_match, cmdide_attach, NULL, NULL);
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static void cmd_chip_map(struct pciide_softc*, struct pci_attach_args*);
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static void cmd0643_9_chip_map(struct pciide_softc*, struct pci_attach_args*);
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static void cmd0643_9_setup_channel(struct ata_channel*);
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static void cmd_channel_map(struct pci_attach_args *, struct pciide_softc *,
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int);
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static int cmd_pci_intr(void *);
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static void cmd646_9_irqack(struct ata_channel *);
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static void cmd680_chip_map(struct pciide_softc*, struct pci_attach_args*);
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static void cmd680_setup_channel(struct ata_channel*);
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static void cmd680_channel_map(struct pci_attach_args *, struct pciide_softc *,
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int);
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static const struct pciide_product_desc pciide_cmd_products[] = {
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{ PCI_PRODUCT_CMDTECH_640,
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0,
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"CMD Technology PCI0640",
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cmd_chip_map
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},
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{ PCI_PRODUCT_CMDTECH_643,
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0,
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"CMD Technology PCI0643",
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cmd0643_9_chip_map,
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},
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{ PCI_PRODUCT_CMDTECH_646,
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0,
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"CMD Technology PCI0646",
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cmd0643_9_chip_map,
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},
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{ PCI_PRODUCT_CMDTECH_648,
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0,
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"CMD Technology PCI0648",
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cmd0643_9_chip_map,
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},
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{ PCI_PRODUCT_CMDTECH_649,
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0,
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"CMD Technology PCI0649",
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cmd0643_9_chip_map,
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},
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{ PCI_PRODUCT_CMDTECH_680,
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0,
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"Silicon Image 0680",
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cmd680_chip_map,
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},
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{ 0,
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0,
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NULL,
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NULL
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}
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};
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static int
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cmdide_match(struct device *parent, struct cfdata *match, void *aux)
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{
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struct pci_attach_args *pa = aux;
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if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) {
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if (pciide_lookup_product(pa->pa_id, pciide_cmd_products))
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return (2);
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}
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return (0);
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}
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static void
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cmdide_attach(struct device *parent, struct device *self, void *aux)
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{
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struct pci_attach_args *pa = aux;
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struct pciide_softc *sc = (struct pciide_softc *)self;
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pciide_common_attach(sc, pa,
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pciide_lookup_product(pa->pa_id, pciide_cmd_products));
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}
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static void
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cmd_channel_map(struct pci_attach_args *pa, struct pciide_softc *sc,
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int channel)
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{
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struct pciide_channel *cp = &sc->pciide_channels[channel];
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bus_size_t cmdsize, ctlsize;
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u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL);
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int interface, one_channel;
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/*
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* The 0648/0649 can be told to identify as a RAID controller.
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* In this case, we have to fake interface
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*/
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if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) {
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interface = PCIIDE_INTERFACE_SETTABLE(0) |
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PCIIDE_INTERFACE_SETTABLE(1);
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if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) &
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CMD_CONF_DSA1)
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interface |= PCIIDE_INTERFACE_PCI(0) |
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PCIIDE_INTERFACE_PCI(1);
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} else {
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interface = PCI_INTERFACE(pa->pa_class);
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}
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sc->wdc_chanarray[channel] = &cp->ata_channel;
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cp->name = PCIIDE_CHANNEL_NAME(channel);
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cp->ata_channel.ch_channel = channel;
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cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
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/*
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* Older CMD64X doesn't have independant channels
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*/
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switch (sc->sc_pp->ide_product) {
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case PCI_PRODUCT_CMDTECH_649:
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one_channel = 0;
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break;
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default:
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one_channel = 1;
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break;
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}
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if (channel > 0 && one_channel) {
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cp->ata_channel.ch_queue =
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sc->pciide_channels[0].ata_channel.ch_queue;
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} else {
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cp->ata_channel.ch_queue =
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malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT);
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}
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if (cp->ata_channel.ch_queue == NULL) {
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aprint_error("%s %s channel: "
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"can't allocate memory for command queue",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name);
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return;
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}
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aprint_normal("%s: %s channel %s to %s mode\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name,
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(interface & PCIIDE_INTERFACE_SETTABLE(channel)) ?
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"configured" : "wired",
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(interface & PCIIDE_INTERFACE_PCI(channel)) ?
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"native-PCI" : "compatibility");
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/*
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* with a CMD PCI64x, if we get here, the first channel is enabled:
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* there's no way to disable the first channel without disabling
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* the whole device
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*/
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if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) {
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aprint_normal("%s: %s channel ignored (disabled)\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name);
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cp->ata_channel.ch_flags |= ATACH_DISABLED;
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return;
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}
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pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr);
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}
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static int
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cmd_pci_intr(void *arg)
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{
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struct pciide_softc *sc = arg;
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struct pciide_channel *cp;
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struct ata_channel *wdc_cp;
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int i, rv, crv;
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u_int32_t priirq, secirq;
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rv = 0;
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priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF);
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secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23);
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for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
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cp = &sc->pciide_channels[i];
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wdc_cp = &cp->ata_channel;
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/* If a compat channel skip. */
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if (cp->compat)
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continue;
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if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) ||
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(i == 1 && (secirq & CMD_ARTTIM23_IRQ))) {
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crv = wdcintr(wdc_cp);
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if (crv == 0) {
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printf("%s:%d: bogus intr\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, i);
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sc->sc_wdcdev.irqack(wdc_cp);
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} else
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rv = 1;
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}
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}
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return rv;
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}
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static void
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cmd_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
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{
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int channel;
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/*
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* For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE
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* and base addresses registers can be disabled at
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* hardware level. In this case, the device is wired
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* in compat mode and its first channel is always enabled,
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* but we can't rely on PCI_COMMAND_IO_ENABLE.
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* In fact, it seems that the first channel of the CMD PCI0640
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* can't be disabled.
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*/
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#ifdef PCIIDE_CMD064x_DISABLE
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if (pciide_chipen(sc, pa) == 0)
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return;
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#endif
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aprint_normal("%s: hardware does not support DMA\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
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sc->sc_dma_ok = 0;
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sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
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sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
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sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16;
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wdc_allocate_regs(&sc->sc_wdcdev);
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for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
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channel++) {
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cmd_channel_map(pa, sc, channel);
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}
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}
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static void
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cmd0643_9_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
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{
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int channel;
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pcireg_t rev = PCI_REVISION(pa->pa_class);
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/*
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* For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE
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* and base addresses registers can be disabled at
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* hardware level. In this case, the device is wired
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* in compat mode and its first channel is always enabled,
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* but we can't rely on PCI_COMMAND_IO_ENABLE.
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* In fact, it seems that the first channel of the CMD PCI0640
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* can't be disabled.
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*/
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#ifdef PCIIDE_CMD064x_DISABLE
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if (pciide_chipen(sc, pa) == 0)
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return;
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#endif
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aprint_normal("%s: bus-master DMA support present",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
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pciide_mapreg_dma(sc, pa);
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aprint_normal("\n");
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sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
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if (sc->sc_dma_ok) {
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
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switch (sc->sc_pp->ide_product) {
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case PCI_PRODUCT_CMDTECH_649:
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
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sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
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sc->sc_wdcdev.irqack = cmd646_9_irqack;
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break;
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case PCI_PRODUCT_CMDTECH_648:
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
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sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
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sc->sc_wdcdev.irqack = cmd646_9_irqack;
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break;
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case PCI_PRODUCT_CMDTECH_646:
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if (rev >= CMD0646U2_REV) {
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
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sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
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} else if (rev >= CMD0646U_REV) {
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/*
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* Linux's driver claims that the 646U is broken
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* with UDMA. Only enable it if we know what we're
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* doing
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*/
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#ifdef PCIIDE_CMD0646U_ENABLEUDMA
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
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sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
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#endif
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/* explicitly disable UDMA */
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pciide_pci_write(sc->sc_pc, sc->sc_tag,
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CMD_UDMATIM(0), 0);
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pciide_pci_write(sc->sc_pc, sc->sc_tag,
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CMD_UDMATIM(1), 0);
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}
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sc->sc_wdcdev.irqack = cmd646_9_irqack;
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break;
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default:
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sc->sc_wdcdev.irqack = pciide_irqack;
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}
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}
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sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
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sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
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sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
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sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
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sc->sc_wdcdev.sc_atac.atac_set_modes = cmd0643_9_setup_channel;
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ATADEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n",
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pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54),
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pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)),
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DEBUG_PROBE);
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wdc_allocate_regs(&sc->sc_wdcdev);
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for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
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channel++)
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cmd_channel_map(pa, sc, channel);
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/*
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* note - this also makes sure we clear the irq disable and reset
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* bits
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*/
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pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE);
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ATADEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n",
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pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54),
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pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)),
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DEBUG_PROBE);
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}
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static void
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cmd0643_9_setup_channel(struct ata_channel *chp)
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{
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struct ata_drive_datas *drvp;
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u_int8_t tim;
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u_int32_t idedma_ctl, udma_reg;
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int drive, s;
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struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
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struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
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idedma_ctl = 0;
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/* setup DMA if needed */
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pciide_channel_dma_setup(cp);
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for (drive = 0; drive < 2; drive++) {
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drvp = &chp->ch_drive[drive];
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/* If no drive, skip */
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if ((drvp->drive_flags & DRIVE) == 0)
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continue;
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/* add timing values, setup DMA if needed */
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tim = cmd0643_9_data_tim_pio[drvp->PIO_mode];
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if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) {
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if (drvp->drive_flags & DRIVE_UDMA) {
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/* UltraDMA on a 646U2, 0648 or 0649 */
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s = splbio();
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drvp->drive_flags &= ~DRIVE_DMA;
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splx(s);
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udma_reg = pciide_pci_read(sc->sc_pc,
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sc->sc_tag, CMD_UDMATIM(chp->ch_channel));
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if (drvp->UDMA_mode > 2 &&
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(pciide_pci_read(sc->sc_pc, sc->sc_tag,
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CMD_BICSR) &
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CMD_BICSR_80(chp->ch_channel)) == 0)
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drvp->UDMA_mode = 2;
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if (drvp->UDMA_mode > 2)
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udma_reg &= ~CMD_UDMATIM_UDMA33(drive);
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else if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 2)
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udma_reg |= CMD_UDMATIM_UDMA33(drive);
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udma_reg |= CMD_UDMATIM_UDMA(drive);
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udma_reg &= ~(CMD_UDMATIM_TIM_MASK <<
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CMD_UDMATIM_TIM_OFF(drive));
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udma_reg |=
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(cmd0646_9_tim_udma[drvp->UDMA_mode] <<
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CMD_UDMATIM_TIM_OFF(drive));
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pciide_pci_write(sc->sc_pc, sc->sc_tag,
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CMD_UDMATIM(chp->ch_channel), udma_reg);
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} else {
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/*
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* use Multiword DMA.
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* Timings will be used for both PIO and DMA,
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* so adjust DMA mode if needed
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* if we have a 0646U2/8/9, turn off UDMA
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*/
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if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) {
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udma_reg = pciide_pci_read(sc->sc_pc,
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sc->sc_tag,
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CMD_UDMATIM(chp->ch_channel));
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udma_reg &= ~CMD_UDMATIM_UDMA(drive);
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pciide_pci_write(sc->sc_pc, sc->sc_tag,
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CMD_UDMATIM(chp->ch_channel),
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udma_reg);
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}
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if (drvp->PIO_mode >= 3 &&
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(drvp->DMA_mode + 2) > drvp->PIO_mode) {
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drvp->DMA_mode = drvp->PIO_mode - 2;
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}
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tim = cmd0643_9_data_tim_dma[drvp->DMA_mode];
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}
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idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
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}
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pciide_pci_write(sc->sc_pc, sc->sc_tag,
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CMD_DATA_TIM(chp->ch_channel, drive), tim);
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}
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if (idedma_ctl != 0) {
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/* Add software bits in status register */
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bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
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idedma_ctl);
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}
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}
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static void
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cmd646_9_irqack(struct ata_channel *chp)
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{
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u_int32_t priirq, secirq;
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struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
|
|
|
|
if (chp->ch_channel == 0) {
|
|
priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF);
|
|
pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq);
|
|
} else {
|
|
secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23);
|
|
pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq);
|
|
}
|
|
pciide_irqack(chp);
|
|
}
|
|
|
|
static void
|
|
cmd680_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
|
|
{
|
|
int channel;
|
|
|
|
if (pciide_chipen(sc, pa) == 0)
|
|
return;
|
|
|
|
aprint_normal("%s: bus-master DMA support present",
|
|
sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
|
|
pciide_mapreg_dma(sc, pa);
|
|
aprint_normal("\n");
|
|
sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
|
|
if (sc->sc_dma_ok) {
|
|
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
|
|
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
|
|
sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
|
|
sc->sc_wdcdev.irqack = pciide_irqack;
|
|
}
|
|
|
|
sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
|
|
sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
|
|
sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
|
|
sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
|
|
sc->sc_wdcdev.sc_atac.atac_set_modes = cmd680_setup_channel;
|
|
|
|
pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x80, 0x00);
|
|
pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x84, 0x00);
|
|
pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x8a,
|
|
pciide_pci_read(sc->sc_pc, sc->sc_tag, 0x8a) | 0x01);
|
|
|
|
wdc_allocate_regs(&sc->sc_wdcdev);
|
|
|
|
for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
|
|
channel++)
|
|
cmd680_channel_map(pa, sc, channel);
|
|
}
|
|
|
|
static void
|
|
cmd680_channel_map(struct pci_attach_args *pa, struct pciide_softc *sc,
|
|
int channel)
|
|
{
|
|
struct pciide_channel *cp = &sc->pciide_channels[channel];
|
|
bus_size_t cmdsize, ctlsize;
|
|
int interface, i, reg;
|
|
static const u_int8_t init_val[] =
|
|
{ 0x8a, 0x32, 0x8a, 0x32, 0x8a, 0x32,
|
|
0x92, 0x43, 0x92, 0x43, 0x09, 0x40, 0x09, 0x40 };
|
|
|
|
if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) {
|
|
interface = PCIIDE_INTERFACE_SETTABLE(0) |
|
|
PCIIDE_INTERFACE_SETTABLE(1);
|
|
interface |= PCIIDE_INTERFACE_PCI(0) |
|
|
PCIIDE_INTERFACE_PCI(1);
|
|
} else {
|
|
interface = PCI_INTERFACE(pa->pa_class);
|
|
}
|
|
|
|
sc->wdc_chanarray[channel] = &cp->ata_channel;
|
|
cp->name = PCIIDE_CHANNEL_NAME(channel);
|
|
cp->ata_channel.ch_channel = channel;
|
|
cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
|
|
|
|
cp->ata_channel.ch_queue =
|
|
malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT);
|
|
if (cp->ata_channel.ch_queue == NULL) {
|
|
aprint_error("%s %s channel: "
|
|
"can't allocate memory for command queue",
|
|
sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name);
|
|
return;
|
|
}
|
|
|
|
/* XXX */
|
|
reg = 0xa2 + channel * 16;
|
|
for (i = 0; i < sizeof(init_val); i++)
|
|
pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]);
|
|
|
|
aprint_normal("%s: %s channel %s to %s mode\n",
|
|
sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name,
|
|
(interface & PCIIDE_INTERFACE_SETTABLE(channel)) ?
|
|
"configured" : "wired",
|
|
(interface & PCIIDE_INTERFACE_PCI(channel)) ?
|
|
"native-PCI" : "compatibility");
|
|
|
|
pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, pciide_pci_intr);
|
|
}
|
|
|
|
static void
|
|
cmd680_setup_channel(struct ata_channel *chp)
|
|
{
|
|
struct ata_drive_datas *drvp;
|
|
u_int8_t mode, off, scsc;
|
|
u_int16_t val;
|
|
u_int32_t idedma_ctl;
|
|
int drive, s;
|
|
struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
|
|
struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
|
|
pci_chipset_tag_t pc = sc->sc_pc;
|
|
pcitag_t pa = sc->sc_tag;
|
|
static const u_int8_t udma2_tbl[] =
|
|
{ 0x0f, 0x0b, 0x07, 0x06, 0x03, 0x02, 0x01 };
|
|
static const u_int8_t udma_tbl[] =
|
|
{ 0x0c, 0x07, 0x05, 0x04, 0x02, 0x01, 0x00 };
|
|
static const u_int16_t dma_tbl[] =
|
|
{ 0x2208, 0x10c2, 0x10c1 };
|
|
static const u_int16_t pio_tbl[] =
|
|
{ 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
|
|
|
|
idedma_ctl = 0;
|
|
pciide_channel_dma_setup(cp);
|
|
mode = pciide_pci_read(pc, pa, 0x80 + chp->ch_channel * 4);
|
|
|
|
for (drive = 0; drive < 2; drive++) {
|
|
drvp = &chp->ch_drive[drive];
|
|
/* If no drive, skip */
|
|
if ((drvp->drive_flags & DRIVE) == 0)
|
|
continue;
|
|
mode &= ~(0x03 << (drive * 4));
|
|
if (drvp->drive_flags & DRIVE_UDMA) {
|
|
s = splbio();
|
|
drvp->drive_flags &= ~DRIVE_DMA;
|
|
splx(s);
|
|
off = 0xa0 + chp->ch_channel * 16;
|
|
if (drvp->UDMA_mode > 2 &&
|
|
(pciide_pci_read(pc, pa, off) & 0x01) == 0)
|
|
drvp->UDMA_mode = 2;
|
|
scsc = pciide_pci_read(pc, pa, 0x8a);
|
|
if (drvp->UDMA_mode == 6 && (scsc & 0x30) == 0) {
|
|
pciide_pci_write(pc, pa, 0x8a, scsc | 0x01);
|
|
scsc = pciide_pci_read(pc, pa, 0x8a);
|
|
if ((scsc & 0x30) == 0)
|
|
drvp->UDMA_mode = 5;
|
|
}
|
|
mode |= 0x03 << (drive * 4);
|
|
off = 0xac + chp->ch_channel * 16 + drive * 2;
|
|
val = pciide_pci_read(pc, pa, off) & ~0x3f;
|
|
if (scsc & 0x30)
|
|
val |= udma2_tbl[drvp->UDMA_mode];
|
|
else
|
|
val |= udma_tbl[drvp->UDMA_mode];
|
|
pciide_pci_write(pc, pa, off, val);
|
|
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
|
|
} else if (drvp->drive_flags & DRIVE_DMA) {
|
|
mode |= 0x02 << (drive * 4);
|
|
off = 0xa8 + chp->ch_channel * 16 + drive * 2;
|
|
val = dma_tbl[drvp->DMA_mode];
|
|
pciide_pci_write(pc, pa, off, val & 0xff);
|
|
pciide_pci_write(pc, pa, off, val >> 8);
|
|
idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
|
|
} else {
|
|
mode |= 0x01 << (drive * 4);
|
|
off = 0xa4 + chp->ch_channel * 16 + drive * 2;
|
|
val = pio_tbl[drvp->PIO_mode];
|
|
pciide_pci_write(pc, pa, off, val & 0xff);
|
|
pciide_pci_write(pc, pa, off, val >> 8);
|
|
}
|
|
}
|
|
|
|
pciide_pci_write(pc, pa, 0x80 + chp->ch_channel * 4, mode);
|
|
if (idedma_ctl != 0) {
|
|
/* Add software bits in status register */
|
|
bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
|
|
idedma_ctl);
|
|
}
|
|
}
|