cf15785585
This patch adds the symbol names to icu.s that vmstat expects
the interrupt counters to be called. It also adds code to config
so that the names of the interrupts are written at the end of vectors.s
so vmstat can report real device names. It also cleans up and enables
the logging of stray interrupts. The counters for false interrupts
are added but the fix for them is not (the fix I have is not done
very good.) A false interrupt is when a device asserts it's interrupt
signal, then removes it before the 8259 can latch it. This is the number
one cause of stray IRQ7's and IRQ15's.
Additional device probe information is now printed. This includes
ending I/O address (many drivers do not return the correct value from a
probe this still needs to be fixed), memory address and size, driver
flags passed in by config.
593 lines
16 KiB
C
593 lines
16 KiB
C
/*-
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* Copyright (c) 1991 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)isa.c 7.2 (Berkeley) 5/13/91
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*/
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static char rcsid[] = "$Header: /cvsroot/src/sys/dev/isa/isa.c,v 1.4 1993/04/09 13:43:40 cgd Exp $";
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/*
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* code to manage AT bus
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*
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* 92/08/18 Frank P. MacLachlan (fpm@crash.cts.com):
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* Fixed uninitialized variable problem and added code to deal
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* with DMA page boundaries in isa_dmarangecheck(). Fixed word
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* mode DMA count compution and reorganized DMA setup code in
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* isa_dmastart()
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*/
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#include "param.h"
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#include "systm.h"
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#include "conf.h"
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#include "file.h"
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#include "buf.h"
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#include "uio.h"
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#include "syslog.h"
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#include "malloc.h"
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#include "rlist.h"
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#include "machine/segments.h"
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#include "vm/vm.h"
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#include "i386/isa/isa_device.h"
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#include "i386/isa/isa.h"
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#include "i386/isa/icu.h"
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#include "i386/isa/ic/i8237.h"
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#include "i386/isa/ic/i8042.h"
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/*
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** Register definitions for DMA controller 1 (channels 0..3):
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*/
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#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */
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#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */
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#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */
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#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */
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/*
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** Register definitions for DMA controller 2 (channels 4..7):
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*/
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#define DMA2_CHN(c) (IO_DMA1 + 2*(2*(c))) /* addr reg for channel c */
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#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */
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#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */
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#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */
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int config_isadev(struct isa_device *, u_short *);
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#ifdef notyet
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struct rlist *isa_iomem;
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/*
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* Configure all ISA devices
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*/
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isa_configure() {
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struct isa_device *dvp;
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struct isa_driver *dp;
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splhigh();
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INTREN(IRQ_SLAVE);
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/*rlist_free(&isa_iomem, 0xa0000, 0xfffff);*/
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for (dvp = isa_devtab_tty; dvp; dvp++)
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(void) config_isadev(dvp, &ttymask);
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for (dvp = isa_devtab_bio; dvp; dvp++)
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(void) config_isadev(dvp, &biomask);
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for (dvp = isa_devtab_net; dvp; dvp++)
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(void) config_isadev(dvp, &netmask);
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for (dvp = isa_devtab_null; dvp; dvp++)
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(void) config_isadev(dvp, 0);
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#include "sl.h"
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#if NSL > 0
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netmask |= ttymask;
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ttymask |= netmask;
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#endif
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/* printf("biomask %x ttymask %x netmask %x\n", biomask, ttymask, netmask); */
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splnone();
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}
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/*
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* Configure an ISA device.
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*/
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config_isadev(isdp, mp)
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struct isa_device *isdp;
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u_short *mp;
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{
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struct isa_driver *dp;
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static short drqseen, irqseen;
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if (dp = isdp->id_driver) {
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/* if a device with i/o memory, convert to virtual address */
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if (isdp->id_maddr) {
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extern unsigned int atdevbase;
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isdp->id_maddr -= IOM_BEGIN;
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isdp->id_maddr += atdevbase;
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}
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isdp->id_alive = (*dp->probe)(isdp);
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if (isdp->id_alive) {
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printf("%s%d at port 0x%x ", dp->name,
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isdp->id_unit, isdp->id_iobase);
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/* check for conflicts */
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if (irqseen & isdp->id_irq) {
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printf("INTERRUPT CONFLICT - irq%d\n",
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ffs(isdp->id_irq) - 1);
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return (0);
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}
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if (isdp->id_drq != -1
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&& (drqseen & (1<<isdp->id_drq))) {
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printf("DMA CONFLICT - drq%d\n", isdp->id_drq);
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return (0);
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}
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/* NEED TO CHECK IOMEM CONFLICT HERE */
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/* allocate and wire in device */
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if(isdp->id_irq) {
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int intrno;
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intrno = ffs(isdp->id_irq)-1;
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printf("irq %d ", intrno);
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INTREN(isdp->id_irq);
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if(mp)INTRMASK(*mp,isdp->id_irq);
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setidt(NRSVIDT + intrno, isdp->id_intr,
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SDT_SYS386IGT, SEL_KPL);
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irqseen |= isdp->id_irq;
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}
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if (isdp->id_drq != -1) {
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printf("drq %d ", isdp->id_drq);
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drqseen |= 1 << isdp->id_drq;
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}
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(*dp->attach)(isdp);
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printf("on isa\n");
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}
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return (1);
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} else return(0);
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}
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#else /* notyet */
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/*
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* Configure all ISA devices
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*/
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isa_configure() {
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struct isa_device *dvp;
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struct isa_driver *dp;
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splhigh();
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INTREN(IRQ_SLAVE);
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for (dvp = isa_devtab_tty; config_isadev(dvp,&ttymask); dvp++);
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for (dvp = isa_devtab_bio; config_isadev(dvp,&biomask); dvp++);
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for (dvp = isa_devtab_net; config_isadev(dvp,&netmask); dvp++);
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for (dvp = isa_devtab_null; config_isadev(dvp,0); dvp++);
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#include "sl.h"
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#if NSL > 0
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netmask |= ttymask;
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ttymask |= netmask;
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#endif
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/* biomask |= ttymask ; can some tty devices use buffers? */
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/* printf("biomask %x ttymask %x netmask %x\n", biomask, ttymask, netmask); */
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splnone();
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}
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/*
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* Configure an ISA device.
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*/
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config_isadev(isdp, mp)
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struct isa_device *isdp;
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u_short *mp;
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{
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struct isa_driver *dp;
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if (dp = isdp->id_driver) {
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if (isdp->id_maddr) {
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extern u_int atdevbase;
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isdp->id_maddr -= 0xa0000;
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isdp->id_maddr += atdevbase;
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}
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isdp->id_alive = (*dp->probe)(isdp);
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if (isdp->id_alive) {
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printf("%s%d", dp->name, isdp->id_unit);
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printf(" at 0x%x-0x%x ", isdp->id_iobase,
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isdp->id_iobase + isdp->id_alive);
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if(isdp->id_irq)
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printf("irq %d ", ffs(isdp->id_irq)-1);
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if (isdp->id_drq != -1)
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printf("drq %d ", isdp->id_drq);
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if (isdp->id_maddr != 0)
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printf("maddr 0x%x ", kvtop(isdp->id_maddr));
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if (isdp->id_msize != 0)
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printf("msize %d ", isdp->id_msize);
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if (isdp->id_flags != 0)
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printf("flags 0x%x ", isdp->id_flags);
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printf("on isa\n");
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(*dp->attach)(isdp);
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if(isdp->id_irq) {
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int intrno;
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intrno = ffs(isdp->id_irq)-1;
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INTREN(isdp->id_irq);
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if(mp)
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INTRMASK(*mp,isdp->id_irq);
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setidt(ICU_OFFSET+intrno, isdp->id_intr,
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SDT_SYS386IGT, SEL_KPL);
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}
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}
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return (1);
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} else return(0);
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}
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#endif /* (!) notyet */
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#define IDTVEC(name) __CONCAT(X,name)
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/* default interrupt vector table entries */
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extern IDTVEC(intr0), IDTVEC(intr1), IDTVEC(intr2), IDTVEC(intr3),
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IDTVEC(intr4), IDTVEC(intr5), IDTVEC(intr6), IDTVEC(intr7),
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IDTVEC(intr8), IDTVEC(intr9), IDTVEC(intr10), IDTVEC(intr11),
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IDTVEC(intr12), IDTVEC(intr13), IDTVEC(intr14), IDTVEC(intr15);
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static *defvec[16] = {
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&IDTVEC(intr0), &IDTVEC(intr1), &IDTVEC(intr2), &IDTVEC(intr3),
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&IDTVEC(intr4), &IDTVEC(intr5), &IDTVEC(intr6), &IDTVEC(intr7),
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&IDTVEC(intr8), &IDTVEC(intr9), &IDTVEC(intr10), &IDTVEC(intr11),
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&IDTVEC(intr12), &IDTVEC(intr13), &IDTVEC(intr14), &IDTVEC(intr15) };
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/* out of range default interrupt vector gate entry */
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extern IDTVEC(intrdefault);
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/*
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* Fill in default interrupt table (in case of spuruious interrupt
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* during configuration of kernel, setup interrupt control unit
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*/
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isa_defaultirq() {
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int i;
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/* icu vectors */
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for (i = NRSVIDT ; i < NRSVIDT+ICU_LEN ; i++)
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setidt(i, defvec[i], SDT_SYS386IGT, SEL_KPL);
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/* out of range vectors */
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for (i = NRSVIDT; i < NIDT; i++)
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setidt(i, &IDTVEC(intrdefault), SDT_SYS386IGT, SEL_KPL);
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/* clear npx intr latch */
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outb(0xf1,0);
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/* initialize 8259's */
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outb(IO_ICU1, 0x11); /* reset; program device, four bytes */
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outb(IO_ICU1+1, NRSVIDT); /* starting at this vector index */
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outb(IO_ICU1+1, 1<<2); /* slave on line 2 */
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outb(IO_ICU1+1, 1); /* 8086 mode */
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outb(IO_ICU1+1, 0xff); /* leave interrupts masked */
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outb(IO_ICU1, 2); /* default to ISR on read */
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outb(IO_ICU2, 0x11); /* reset; program device, four bytes */
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outb(IO_ICU2+1, NRSVIDT+8); /* staring at this vector index */
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outb(IO_ICU2+1,2); /* my slave id is 2 */
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outb(IO_ICU2+1,1); /* 8086 mode */
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outb(IO_ICU2+1, 0xff); /* leave interrupts masked */
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outb(IO_ICU2, 2); /* default to ISR on read */
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}
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/* region of physical memory known to be contiguous */
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vm_offset_t isaphysmem;
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static caddr_t dma_bounce[8]; /* XXX */
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static char bounced[8]; /* XXX */
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#define MAXDMASZ 512 /* XXX */
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/* high byte of address is stored in this port for i-th dma channel */
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static short dmapageport[8] =
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{ 0x87, 0x83, 0x81, 0x82, 0x8f, 0x8b, 0x89, 0x8a };
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/*
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* isa_dmacascade(): program 8237 DMA controller channel to accept
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* external dma control by a board.
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*/
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void isa_dmacascade(unsigned chan)
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{
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if (chan > 7)
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panic("isa_dmacascade: impossible request");
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/* set dma channel mode, and set dma channel mode */
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if ((chan & 4) == 0) {
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outb(DMA1_MODE, DMA37MD_CASCADE | chan);
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outb(DMA1_SMSK, chan);
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} else {
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outb(DMA2_MODE, DMA37MD_CASCADE | (chan & 3));
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outb(DMA2_SMSK, chan & 3);
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}
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}
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/*
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* isa_dmastart(): program 8237 DMA controller channel, avoid page alignment
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* problems by using a bounce buffer.
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*/
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void isa_dmastart(int flags, caddr_t addr, unsigned nbytes, unsigned chan)
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{ vm_offset_t phys;
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int waport;
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caddr_t newaddr;
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if ( chan > 7
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|| (chan < 4 && nbytes > (1<<16))
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|| (chan >= 4 && (nbytes > (1<<17) || (u_int)addr & 1)))
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panic("isa_dmastart: impossible request");
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if (isa_dmarangecheck(addr, nbytes, chan)) {
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if (dma_bounce[chan] == 0)
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dma_bounce[chan] =
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/*(caddr_t)malloc(MAXDMASZ, M_TEMP, M_WAITOK);*/
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(caddr_t) isaphysmem + NBPG*chan;
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bounced[chan] = 1;
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newaddr = dma_bounce[chan];
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*(int *) newaddr = 0; /* XXX */
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/* copy bounce buffer on write */
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if (!(flags & B_READ))
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bcopy(addr, newaddr, nbytes);
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addr = newaddr;
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}
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/* translate to physical */
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phys = pmap_extract(pmap_kernel(), (vm_offset_t)addr);
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if ((chan & 4) == 0) {
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/*
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* Program one of DMA channels 0..3. These are
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* byte mode channels.
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*/
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/* set dma channel mode, and reset address ff */
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if (flags & B_READ)
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outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|chan);
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else
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outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_READ|chan);
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outb(DMA1_FFC, 0);
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/* send start address */
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waport = DMA1_CHN(chan);
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outb(waport, phys);
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outb(waport, phys>>8);
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outb(dmapageport[chan], phys>>16);
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/* send count */
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outb(waport + 1, --nbytes);
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outb(waport + 1, nbytes>>8);
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/* unmask channel */
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outb(DMA1_SMSK, chan);
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} else {
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/*
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* Program one of DMA channels 4..7. These are
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* word mode channels.
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*/
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/* set dma channel mode, and reset address ff */
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if (flags & B_READ)
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outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|(chan&3));
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else
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outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_READ|(chan&3));
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outb(DMA2_FFC, 0);
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/* send start address */
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waport = DMA2_CHN(chan - 4);
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outb(waport, phys>>1);
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outb(waport, phys>>9);
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outb(dmapageport[chan], phys>>16);
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/* send count */
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nbytes >>= 1;
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outb(waport + 2, --nbytes);
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outb(waport + 2, nbytes>>8);
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/* unmask channel */
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outb(DMA2_SMSK, chan & 3);
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}
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}
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void isa_dmadone(int flags, caddr_t addr, int nbytes, int chan)
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{
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/* copy bounce buffer on read */
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/*if ((flags & (B_PHYS|B_READ)) == (B_PHYS|B_READ))*/
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if (bounced[chan]) {
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bcopy(dma_bounce[chan], addr, nbytes);
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bounced[chan] = 0;
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}
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}
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/*
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* Check for problems with the address range of a DMA transfer
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* (non-contiguous physical pages, outside of bus address space,
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* crossing DMA page boundaries).
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* Return true if special handling needed.
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*/
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isa_dmarangecheck(caddr_t va, unsigned length, unsigned chan) {
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vm_offset_t phys, priorpage = 0, endva;
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u_int dma_pgmsk = (chan & 4) ? ~(128*1024-1) : ~(64*1024-1);
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endva = (vm_offset_t)round_page(va + length);
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for (; va < (caddr_t) endva ; va += NBPG) {
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phys = trunc_page(pmap_extract(pmap_kernel(), (vm_offset_t)va));
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#define ISARAM_END RAM_END
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if (phys == 0)
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panic("isa_dmacheck: no physical page present");
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if (phys > ISARAM_END)
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return (1);
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if (priorpage) {
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if (priorpage + NBPG != phys)
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return (1);
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/* check if crossing a DMA page boundary */
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if (((u_int)priorpage ^ (u_int)phys) & dma_pgmsk)
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return (1);
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}
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priorpage = phys;
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}
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return (0);
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}
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/* head of queue waiting for physmem to become available */
|
|
struct buf isa_physmemq;
|
|
|
|
/* blocked waiting for resource to become free for exclusive use */
|
|
static isaphysmemflag;
|
|
/* if waited for and call requested when free (B_CALL) */
|
|
static void (*isaphysmemunblock)(); /* needs to be a list */
|
|
|
|
/*
|
|
* Allocate contiguous physical memory for transfer, returning
|
|
* a *virtual* address to region. May block waiting for resource.
|
|
* (assumed to be called at splbio())
|
|
*/
|
|
caddr_t
|
|
isa_allocphysmem(caddr_t va, unsigned length, void (*func)()) {
|
|
|
|
isaphysmemunblock = func;
|
|
while (isaphysmemflag & B_BUSY) {
|
|
isaphysmemflag |= B_WANTED;
|
|
sleep(&isaphysmemflag, PRIBIO);
|
|
}
|
|
isaphysmemflag |= B_BUSY;
|
|
|
|
return((caddr_t)isaphysmem);
|
|
}
|
|
|
|
/*
|
|
* Free contiguous physical memory used for transfer.
|
|
* (assumed to be called at splbio())
|
|
*/
|
|
void
|
|
isa_freephysmem(caddr_t va, unsigned length) {
|
|
|
|
isaphysmemflag &= ~B_BUSY;
|
|
if (isaphysmemflag & B_WANTED) {
|
|
isaphysmemflag &= B_WANTED;
|
|
wakeup(&isaphysmemflag);
|
|
if (isaphysmemunblock)
|
|
(*isaphysmemunblock)();
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Handle a NMI, possibly a machine check.
|
|
* return true to panic system, false to ignore.
|
|
*/
|
|
isa_nmi(cd) {
|
|
|
|
log(LOG_CRIT, "\nNMI port 61 %x, port 70 %x\n", inb(0x61), inb(0x70));
|
|
return(0);
|
|
}
|
|
|
|
/*
|
|
* Caught a stray interrupt, notify
|
|
*/
|
|
isa_strayintr(d) {
|
|
|
|
/* DON'T BOTHER FOR NOW! */
|
|
/* for some reason, we get bursts of intr #7, even if not enabled! */
|
|
/*
|
|
* Well the reason you got bursts of intr #7 is because someone
|
|
* raised an interrupt line and dropped it before the 8259 could
|
|
* prioritize it. This is documented in the intel data book. This
|
|
* means you have BAD hardware! I have changed this so that only
|
|
* the first 10 get logged, then it quits logging them, and puts
|
|
* out a special message. rgrimes 3/25/1993
|
|
*/
|
|
extern u_long isa_stray_intrcnt;
|
|
|
|
isa_stray_intrcnt++;
|
|
if (isa_stray_intrcnt <= 10)
|
|
log(LOG_ERR,"ISA strayintr %x\n", d);
|
|
if (isa_stray_intrcnt == 10)
|
|
log(LOG_CRIT,"Too many ISA strayintr not logging any more\n");
|
|
}
|
|
|
|
/*
|
|
* Wait "n" microseconds. Relies on timer 0 to have 1Mhz clock, regardless
|
|
* of processor board speed. Note: timer had better have been programmed
|
|
* before this is first used!
|
|
*/
|
|
DELAY(n) {
|
|
int tick = getit(0,0) & 1;
|
|
|
|
while (n--) {
|
|
/* wait approximately 1 micro second */
|
|
while (tick == getit(0,0) & 1) ;
|
|
|
|
tick = getit(0,0) & 1;
|
|
}
|
|
}
|
|
|
|
getit(unit, timer) {
|
|
int port = (unit ? IO_TIMER2 : IO_TIMER1) + timer, val;
|
|
|
|
val = inb(port);
|
|
val = (inb(port) << 8) + val;
|
|
return (val);
|
|
}
|
|
|
|
extern int hz;
|
|
|
|
static beeping;
|
|
static
|
|
sysbeepstop(f)
|
|
{
|
|
/* disable counter 2 */
|
|
outb(0x61, inb(0x61) & 0xFC);
|
|
if (f)
|
|
timeout(sysbeepstop, 0, f);
|
|
else
|
|
beeping = 0;
|
|
}
|
|
|
|
void sysbeep(int pitch, int period)
|
|
{
|
|
|
|
outb(0x61, inb(0x61) | 3); /* enable counter 2 */
|
|
outb(0x43, 0xb6); /* set command for counter 2, 2 byte write */
|
|
|
|
outb(0x42, pitch);
|
|
outb(0x42, (pitch>>8));
|
|
|
|
if (!beeping) {
|
|
beeping = period;
|
|
timeout(sysbeepstop, period/2, period);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Pass command to keyboard controller (8042)
|
|
*/
|
|
unsigned kbc_8042cmd(val) {
|
|
|
|
while (inb(KBSTATP)&KBS_IBF);
|
|
if (val) outb(KBCMDP, val);
|
|
while (inb(KBSTATP)&KBS_IBF);
|
|
return (inb(KBDATAP));
|
|
}
|