103 lines
4.4 KiB
C
103 lines
4.4 KiB
C
/* $Id: at91spireg.h,v 1.2 2008/07/03 01:15:38 matt Exp $ */
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/* $NetBSD: at91spireg.h,v 1.2 2008/07/03 01:15:38 matt Exp $ */
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/*-
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* Copyright (c) 2007 Embedtronics Oy.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* 3. All advertising materials mentioning features or use of this
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* software must display the following acknowledgements:
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* This product includes software developed by the Urbana-Champaign
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* Independent Media Center.
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* This product includes software developed by Garrett D'Amore.
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* 4. Urbana-Champaign Independent Media Center's name and Garrett
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* D'Amore's name may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT
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* MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT
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* MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _AT91SPIREG_H_
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#define _AT91SPIREG_H_
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#define SPI_CS_COUNT 4
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#define AT91_SPI_SIZE 0x4000U
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#define SPI_CR 0x00U /* 0x00: Control Register */
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#define SPI_MR 0x04U /* 0x04: Mode Register */
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#define SPI_RDR 0x08U /* 0x08: Receive Data Register */
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#define SPI_TDR 0x0CU /* 0x0C: Transmit Data Register */
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#define SPI_SR 0x10U /* 0x10: Status Register */
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#define SPI_IER 0x14U /* 0x14: Interrupt Enable Reg */
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#define SPI_IDR 0x18U /* 0x18: Interrupt Disable Reg */
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#define SPI_IMR 0x1CU /* 0x1C: Interrupt Mask Reg */
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#define SPI_CSR(slv) (0x30U + 4 * (slv)) /* 0x30: Chip Select Regs */
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#define SPI_PDC_BASE 0x100U /* 0x100: PDC */
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/* Control Register bits: */
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#define SPI_CR_SWRST 0x80 /* 1 = Reset the SPI */
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#define SPI_CR_SPIDIS 0x2 /* 1 = disables the SPI */
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#define SPI_CR_SPIEN 0x1 /* 1 = enables the SPI */
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/* Mode Register bits: */
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#define SPI_MR_DLYBCS 0xFF000000 /* delay between chip selects */
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#define SPI_MR_DLYBCS_SHIFT 24
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#define SPI_MR_PCS 0x000F0000 /* peripheral chip select */
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#define SPI_MR_PCS_SHIFT 16
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#define SPI_MR_LLB 0x80 /* 1 = local loopback enabled */
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#define SPI_MR_MODFDIS 0x10 /* 1 = mode fault detection dis */
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#define SPI_MR_DIV32 0x08 /* 1 = SPI operates at MCK/32 */
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#define SPI_MR_PCSDEC 0x04 /* 1 = use 4- to 16-bit decoder */
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#define SPI_MR_PS 0x02 /* 1 = variable peripheral sel. */
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#define SPI_MR_MSTR 0x01 /* 1 = SPI is in Master mode */
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/* Status Register bits: */
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#define SPI_SR_SPIENS 0x10000 /* 1 = SPI is enabled */
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#define SPI_SR_TXBUFE 0x80 /* 1 = TX Buffer empty */
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#define SPI_SR_RXBUFF 0x40 /* 1 = RX buffer full */
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#define SPI_SR_ENDTX 0x20 /* 1 = End of TX buffer */
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#define SPI_SR_ENDRX 0x10 /* 1 = End of RX buffer */
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#define SPI_SR_OVRES 0x08 /* 1 = Overrun occurred */
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#define SPI_SR_MODF 0x04 /* 1 = Mode fault occurred */
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#define SPI_SR_TDRE 0x02 /* 1 = Transmit Data Reg empty */
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#define SPI_SR_RDRF 0x01 /* 1 = Receive Data Reg full */
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/* Chip Select Register: */
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#define SPI_CSR_DLYBCT 0xFF000000
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#define SPI_CSR_DLYBCT_SHIFT 24
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#define SPI_CSR_DLYBS 0x00FF0000
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#define SPI_CSR_DLYBS_SHIFT 16
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#define SPI_CSR_SCBR 0x0000FF00
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#define SPI_CSR_SCBR_SHIFT 8
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#define SPI_CSR_BITS 0x000000F0
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#define SPI_CSR_BITS_8 (0U<<4)
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#define SPI_CSR_BITS_16 (8U<<4)
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#define SPI_CSR_BITS_SHIFT 4
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#define SPI_CSR_NCPHA 0x00000002
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#define SPI_CSR_CPOL 0x00000001
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#define SPI_CSR_RESERVED 0x0000000C
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#endif /* _AT91SPIREG_H_ */
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