523 lines
15 KiB
C
523 lines
15 KiB
C
/* $NetBSD: viaide.c,v 1.11 2004/03/10 22:16:04 bouyer Exp $ */
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/*
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* Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Manuel Bouyer.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pciidereg.h>
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#include <dev/pci/pciidevar.h>
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#include <dev/pci/pciide_apollo_reg.h>
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static int via_pcib_match(struct pci_attach_args *);
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static void via_chip_map(struct pciide_softc *, struct pci_attach_args *);
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static void via_sata_chip_map(struct pciide_softc *,
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struct pci_attach_args *);
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static void via_setup_channel(struct wdc_channel *);
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static int viaide_match(struct device *, struct cfdata *, void *);
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static void viaide_attach(struct device *, struct device *, void *);
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static const struct pciide_product_desc *
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viaide_lookup(pcireg_t);
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CFATTACH_DECL(viaide, sizeof(struct pciide_softc),
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viaide_match, viaide_attach, NULL, NULL);
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static const struct pciide_product_desc pciide_amd_products[] = {
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{ PCI_PRODUCT_AMD_PBC756_IDE,
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0,
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"Advanced Micro Devices AMD756 IDE Controller",
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via_chip_map
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},
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{ PCI_PRODUCT_AMD_PBC766_IDE,
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0,
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"Advanced Micro Devices AMD766 IDE Controller",
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via_chip_map
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},
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{ PCI_PRODUCT_AMD_PBC768_IDE,
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0,
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"Advanced Micro Devices AMD768 IDE Controller",
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via_chip_map
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},
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{ PCI_PRODUCT_AMD_PBC8111_IDE,
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0,
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"Advanced Micro Devices AMD8111 IDE Controller",
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via_chip_map
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},
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{ 0,
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0,
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NULL,
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NULL
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}
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};
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static const struct pciide_product_desc pciide_nvidia_products[] = {
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{ PCI_PRODUCT_NVIDIA_NFORCE_ATA100,
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0,
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"NVIDIA nForce IDE Controller",
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via_chip_map
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},
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{ PCI_PRODUCT_NVIDIA_NFORCE2_ATA133,
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0,
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"NVIDIA nForce2 IDE Controller",
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via_chip_map
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},
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{ PCI_PRODUCT_NVIDIA_NFORCE3_ATA133,
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0,
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"NVIDIA nForce3 IDE Controller",
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via_chip_map
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},
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{ 0,
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0,
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NULL,
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NULL
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}
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};
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static const struct pciide_product_desc pciide_via_products[] = {
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{ PCI_PRODUCT_VIATECH_VT82C586_IDE,
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0,
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NULL,
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via_chip_map,
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},
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{ PCI_PRODUCT_VIATECH_VT82C586A_IDE,
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0,
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NULL,
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via_chip_map,
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},
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{ PCI_PRODUCT_VIATECH_VT8237_SATA,
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0,
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"VIA Technologies VT8237 SATA Controller",
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via_sata_chip_map,
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},
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{ 0,
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0,
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NULL,
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NULL
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}
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};
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static const struct pciide_product_desc *
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viaide_lookup(pcireg_t id)
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{
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switch (PCI_VENDOR(id)) {
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case PCI_VENDOR_VIATECH:
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return (pciide_lookup_product(id, pciide_via_products));
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case PCI_VENDOR_AMD:
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return (pciide_lookup_product(id, pciide_amd_products));
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case PCI_VENDOR_NVIDIA:
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return (pciide_lookup_product(id, pciide_nvidia_products));
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}
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return (NULL);
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}
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static int
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viaide_match(struct device *parent, struct cfdata *match, void *aux)
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{
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struct pci_attach_args *pa = aux;
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if (viaide_lookup(pa->pa_id) != NULL)
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return (2);
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return (0);
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}
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static void
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viaide_attach(struct device *parent, struct device *self, void *aux)
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{
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struct pci_attach_args *pa = aux;
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struct pciide_softc *sc = (struct pciide_softc *)self;
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const struct pciide_product_desc *pp;
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pp = viaide_lookup(pa->pa_id);
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if (pp == NULL)
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panic("viaide_attach");
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pciide_common_attach(sc, pa, pp);
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}
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static int
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via_pcib_match(struct pci_attach_args *pa)
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{
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if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
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PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA &&
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PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH)
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return (1);
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return 0;
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}
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static void
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via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
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{
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struct pciide_channel *cp;
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pcireg_t interface = PCI_INTERFACE(pa->pa_class);
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pcireg_t vendor = PCI_VENDOR(pa->pa_id);
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int channel;
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u_int32_t ideconf;
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bus_size_t cmdsize, ctlsize;
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pcireg_t pcib_id, pcib_class;
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struct pci_attach_args pcib_pa;
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if (pciide_chipen(sc, pa) == 0)
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return;
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switch (vendor) {
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case PCI_VENDOR_VIATECH:
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/*
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* get a PCI tag for the ISA bridge.
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*/
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if (pci_enumerate_bus(
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(struct pci_softc *)sc->sc_wdcdev.sc_dev.dv_parent,
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via_pcib_match, &pcib_pa) == 0)
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goto unknown;
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pcib_id = pcib_pa.pa_id;
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pcib_class = pcib_pa.pa_class;
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aprint_normal("%s: VIA Technologies ",
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sc->sc_wdcdev.sc_dev.dv_xname);
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switch (PCI_PRODUCT(pcib_id)) {
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case PCI_PRODUCT_VIATECH_VT82C586_ISA:
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aprint_normal("VT82C586 (Apollo VP) ");
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if(PCI_REVISION(pcib_class) >= 0x02) {
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aprint_normal("ATA33 controller\n");
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sc->sc_wdcdev.UDMA_cap = 2;
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} else {
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aprint_normal("controller\n");
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sc->sc_wdcdev.UDMA_cap = 0;
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}
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break;
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case PCI_PRODUCT_VIATECH_VT82C596A:
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aprint_normal("VT82C596A (Apollo Pro) ");
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if (PCI_REVISION(pcib_class) >= 0x12) {
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aprint_normal("ATA66 controller\n");
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sc->sc_wdcdev.UDMA_cap = 4;
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} else {
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aprint_normal("ATA33 controller\n");
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sc->sc_wdcdev.UDMA_cap = 2;
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}
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break;
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case PCI_PRODUCT_VIATECH_VT82C686A_ISA:
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aprint_normal("VT82C686A (Apollo KX133) ");
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if (PCI_REVISION(pcib_class) >= 0x40) {
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aprint_normal("ATA100 controller\n");
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sc->sc_wdcdev.UDMA_cap = 5;
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} else {
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aprint_normal("ATA66 controller\n");
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sc->sc_wdcdev.UDMA_cap = 4;
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}
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break;
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case PCI_PRODUCT_VIATECH_VT8231:
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aprint_normal("VT8231 ATA100 controller\n");
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sc->sc_wdcdev.UDMA_cap = 5;
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break;
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case PCI_PRODUCT_VIATECH_VT8233:
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aprint_normal("VT8233 ATA100 controller\n");
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sc->sc_wdcdev.UDMA_cap = 5;
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break;
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case PCI_PRODUCT_VIATECH_VT8233A:
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aprint_normal("VT8233A ATA133 controller\n");
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sc->sc_wdcdev.UDMA_cap = 6;
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break;
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case PCI_PRODUCT_VIATECH_VT8235:
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aprint_normal("VT8235 ATA133 controller\n");
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sc->sc_wdcdev.UDMA_cap = 6;
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break;
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case PCI_PRODUCT_VIATECH_VT8237:
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aprint_normal("VT8237 ATA133 controller\n");
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sc->sc_wdcdev.UDMA_cap = 6;
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break;
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default:
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unknown:
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aprint_normal("unknown VIA ATA controller\n");
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sc->sc_wdcdev.UDMA_cap = 0;
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}
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sc->sc_apo_regbase = APO_VIA_REGBASE;
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break;
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case PCI_VENDOR_AMD:
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switch (sc->sc_pp->ide_product) {
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case PCI_PRODUCT_AMD_PBC8111_IDE:
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sc->sc_wdcdev.UDMA_cap = 6;
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break;
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case PCI_PRODUCT_AMD_PBC766_IDE:
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case PCI_PRODUCT_AMD_PBC768_IDE:
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sc->sc_wdcdev.UDMA_cap = 5;
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break;
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default:
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sc->sc_wdcdev.UDMA_cap = 4;
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}
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sc->sc_apo_regbase = APO_AMD_REGBASE;
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break;
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case PCI_VENDOR_NVIDIA:
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switch (sc->sc_pp->ide_product) {
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case PCI_PRODUCT_NVIDIA_NFORCE_ATA100:
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sc->sc_wdcdev.UDMA_cap = 5;
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break;
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case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133:
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case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133:
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sc->sc_wdcdev.UDMA_cap = 6;
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break;
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}
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sc->sc_apo_regbase = APO_NVIDIA_REGBASE;
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break;
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default:
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panic("via_chip_map: unknown vendor");
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}
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aprint_normal("%s: bus-master DMA support present",
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sc->sc_wdcdev.sc_dev.dv_xname);
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pciide_mapreg_dma(sc, pa);
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aprint_normal("\n");
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sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
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WDC_CAPABILITY_MODE;
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if (sc->sc_dma_ok) {
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sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK;
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sc->sc_wdcdev.irqack = pciide_irqack;
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if (sc->sc_wdcdev.UDMA_cap > 0)
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sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA;
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}
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sc->sc_wdcdev.PIO_cap = 4;
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sc->sc_wdcdev.DMA_cap = 2;
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sc->sc_wdcdev.set_modes = via_setup_channel;
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sc->sc_wdcdev.channels = sc->wdc_chanarray;
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sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
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WDCDEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, "
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"APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n",
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pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)),
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pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)),
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pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)),
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pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))),
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DEBUG_PROBE);
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ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc));
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for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
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cp = &sc->pciide_channels[channel];
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if (pciide_chansetup(sc, channel, interface) == 0)
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continue;
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if ((ideconf & APO_IDECONF_EN(channel)) == 0) {
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aprint_normal("%s: %s channel ignored (disabled)\n",
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sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
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cp->wdc_channel.ch_flags |= WDCF_DISABLED;
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continue;
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}
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pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
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pciide_pci_intr);
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}
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}
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static void
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via_setup_channel(struct wdc_channel *chp)
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{
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u_int32_t udmatim_reg, datatim_reg;
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u_int8_t idedma_ctl;
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int mode, drive;
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struct ata_drive_datas *drvp;
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struct pciide_channel *cp = (struct pciide_channel*)chp;
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struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc;
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struct wdc_softc *wdc = &sc->sc_wdcdev;
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#ifndef PCIIDE_AMD756_ENABLEDMA
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int rev = PCI_REVISION(
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pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG));
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#endif
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idedma_ctl = 0;
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datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc));
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udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc));
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datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel);
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udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel);
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/* setup DMA if needed */
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pciide_channel_dma_setup(cp);
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for (drive = 0; drive < 2; drive++) {
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drvp = &chp->ch_drive[drive];
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/* If no drive, skip */
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if ((drvp->drive_flags & DRIVE) == 0)
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continue;
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/* add timing values, setup DMA if needed */
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if (((drvp->drive_flags & DRIVE_DMA) == 0 &&
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(drvp->drive_flags & DRIVE_UDMA) == 0)) {
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mode = drvp->PIO_mode;
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goto pio;
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}
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if ((wdc->cap & WDC_CAPABILITY_UDMA) &&
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(drvp->drive_flags & DRIVE_UDMA)) {
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/* use Ultra/DMA */
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drvp->drive_flags &= ~DRIVE_DMA;
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udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) |
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APO_UDMA_EN_MTH(chp->ch_channel, drive);
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switch (PCI_VENDOR(sc->sc_pci_id)) {
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case PCI_VENDOR_VIATECH:
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if (sc->sc_wdcdev.UDMA_cap == 6) {
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/* 8233a */
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udmatim_reg |= APO_UDMA_TIME(
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chp->ch_channel,
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drive,
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via_udma133_tim[drvp->UDMA_mode]);
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} else if (sc->sc_wdcdev.UDMA_cap == 5) {
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/* 686b */
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udmatim_reg |= APO_UDMA_TIME(
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chp->ch_channel,
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drive,
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via_udma100_tim[drvp->UDMA_mode]);
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} else if (sc->sc_wdcdev.UDMA_cap == 4) {
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/* 596b or 686a */
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udmatim_reg |= APO_UDMA_CLK66(
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chp->ch_channel);
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udmatim_reg |= APO_UDMA_TIME(
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chp->ch_channel,
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drive,
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via_udma66_tim[drvp->UDMA_mode]);
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} else {
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/* 596a or 586b */
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udmatim_reg |= APO_UDMA_TIME(
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chp->ch_channel,
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drive,
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via_udma33_tim[drvp->UDMA_mode]);
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}
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break;
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case PCI_VENDOR_AMD:
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case PCI_VENDOR_NVIDIA:
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udmatim_reg |= APO_UDMA_TIME(chp->ch_channel,
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drive, amd7x6_udma_tim[drvp->UDMA_mode]);
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break;
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}
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/* can use PIO timings, MW DMA unused */
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mode = drvp->PIO_mode;
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} else {
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/* use Multiword DMA, but only if revision is OK */
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drvp->drive_flags &= ~DRIVE_UDMA;
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#ifndef PCIIDE_AMD756_ENABLEDMA
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/*
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* The workaround doesn't seem to be necessary
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* with all drives, so it can be disabled by
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* PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if
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* triggered.
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*/
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if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD &&
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sc->sc_pp->ide_product ==
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PCI_PRODUCT_AMD_PBC756_IDE &&
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AMD756_CHIPREV_DISABLEDMA(rev)) {
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aprint_normal(
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"%s:%d:%d: multi-word DMA disabled due "
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"to chip revision\n",
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sc->sc_wdcdev.sc_dev.dv_xname,
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chp->ch_channel, drive);
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mode = drvp->PIO_mode;
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drvp->drive_flags &= ~DRIVE_DMA;
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goto pio;
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}
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#endif
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/* mode = min(pio, dma+2) */
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if (drvp->PIO_mode <= (drvp->DMA_mode + 2))
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mode = drvp->PIO_mode;
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else
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mode = drvp->DMA_mode + 2;
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}
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idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
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pio: /* setup PIO mode */
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if (mode <= 2) {
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drvp->DMA_mode = 0;
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drvp->PIO_mode = 0;
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mode = 0;
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} else {
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drvp->PIO_mode = mode;
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drvp->DMA_mode = mode - 2;
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}
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datatim_reg |=
|
|
APO_DATATIM_PULSE(chp->ch_channel, drive,
|
|
apollo_pio_set[mode]) |
|
|
APO_DATATIM_RECOV(chp->ch_channel, drive,
|
|
apollo_pio_rec[mode]);
|
|
}
|
|
if (idedma_ctl != 0) {
|
|
/* Add software bits in status register */
|
|
bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
|
|
idedma_ctl);
|
|
}
|
|
pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg);
|
|
pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg);
|
|
WDCDEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n",
|
|
pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)),
|
|
pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE);
|
|
}
|
|
|
|
static void
|
|
via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
|
|
{
|
|
struct pciide_channel *cp;
|
|
pcireg_t interface = PCI_INTERFACE(pa->pa_class);
|
|
int channel;
|
|
bus_size_t cmdsize, ctlsize;
|
|
|
|
if (pciide_chipen(sc, pa) == 0)
|
|
return;
|
|
|
|
if (interface == 0) {
|
|
WDCDEBUG_PRINT(("via_sata_chip_map interface == 0\n"),
|
|
DEBUG_PROBE);
|
|
interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
|
|
PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
|
|
}
|
|
|
|
aprint_normal("%s: bus-master DMA support present",
|
|
sc->sc_wdcdev.sc_dev.dv_xname);
|
|
pciide_mapreg_dma(sc, pa);
|
|
aprint_normal("\n");
|
|
|
|
if (sc->sc_dma_ok) {
|
|
sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA | WDC_CAPABILITY_DMA |
|
|
WDC_CAPABILITY_IRQACK;
|
|
sc->sc_wdcdev.irqack = pciide_irqack;
|
|
}
|
|
sc->sc_wdcdev.PIO_cap = 4;
|
|
sc->sc_wdcdev.DMA_cap = 2;
|
|
sc->sc_wdcdev.UDMA_cap = 6;
|
|
|
|
sc->sc_wdcdev.channels = sc->wdc_chanarray;
|
|
sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
|
|
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
|
|
WDC_CAPABILITY_MODE;
|
|
sc->sc_wdcdev.set_modes = sata_setup_channel;
|
|
|
|
for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
|
|
cp = &sc->pciide_channels[channel];
|
|
if (pciide_chansetup(sc, channel, interface) == 0)
|
|
continue;
|
|
pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
|
|
pciide_pci_intr);
|
|
}
|
|
}
|