310 lines
14 KiB
C
310 lines
14 KiB
C
/* $NetBSD: bereg.h,v 1.3 1999/12/20 22:19:11 pk Exp $ */
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/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Paul Kranenburg.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1998 Theo de Raadt and Jason L. Wright.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the authors may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* BE Global registers
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*-
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struct be_bregs {
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u_int32_t xif_cfg; // XIF config
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u_int32_t _unused[63]; // reserved
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u_int32_t stat; // status, clear on read
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u_int32_t imask; // interrupt mask
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u_int32_t _unused2[64]; // reserved
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u_int32_t tx_swreset; // tx software reset
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u_int32_t tx_cfg; // tx config
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u_int32_t ipkt_gap1; // inter-packet gap 1
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u_int32_t ipkt_gap2; // inter-packet gap 2
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u_int32_t attempt_limit; // tx attempt limit
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u_int32_t stime; // tx slot time
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u_int32_t preamble_len; // size of tx preamble
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u_int32_t preamble_pattern; // pattern for tx preamble
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u_int32_t tx_sframe_delim; // tx delimiter
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u_int32_t jsize; // jam length
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u_int32_t tx_pkt_max; // tx max pkt size
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u_int32_t tx_pkt_min; // tx min pkt size
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u_int32_t peak_attempt; // count of tx peak attempts
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u_int32_t dt_ctr; // tx defer timer
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u_int32_t nc_ctr; // tx normal collision cntr
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u_int32_t fc_ctr; // tx first-collision cntr
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u_int32_t ex_ctr; // tx excess-collision cntr
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u_int32_t lt_ctr; // tx late-collision cntr
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u_int32_t rand_seed; // tx random number seed
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u_int32_t tx_smachine; // tx state machine
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u_int32_t _unused3[44]; // reserved
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u_int32_t rx_swreset; // rx software reset
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u_int32_t rx_cfg; // rx config register
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u_int32_t rx_pkt_max; // rx max pkt size
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u_int32_t rx_pkt_min; // rx min pkt size
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u_int32_t mac_addr2; // ethernet address 2 (MSB)
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u_int32_t mac_addr1; // ethernet address 1
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u_int32_t mac_addr0; // ethernet address 0 (LSB)
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u_int32_t fr_ctr; // rx frame receive cntr
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u_int32_t gle_ctr; // rx giant-len error cntr
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u_int32_t unale_ctr; // rx unaligned error cntr
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u_int32_t rcrce_ctr; // rx CRC error cntr
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u_int32_t rx_smachine; // rx state machine
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u_int32_t rx_cvalid; // rx code violation
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u_int32_t _unused4; // reserved
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u_int32_t htable3; // hash table 3
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u_int32_t htable2; // hash table 2
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u_int32_t htable1; // hash table 1
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u_int32_t htable0; // hash table 0
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u_int32_t afilter2; // address filter 2
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u_int32_t afilter1; // address filter 1
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u_int32_t afilter0; // address filter 0
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u_int32_t afilter_mask; // address filter mask
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};
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* register indices: */
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#define BE_BRI_XIFCFG (0*4)
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#define BE_BRI_STAT (64*4)
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#define BE_BRI_IMASK (65*4)
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#define BE_BRI_TXCFG (131*4)
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#define BE_BRI_JSIZE (139*4)
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#define BE_BRI_NCCNT (144*4)
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#define BE_BRI_FCCNT (145*4)
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#define BE_BRI_EXCNT (146*4)
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#define BE_BRI_LTCNT (147*4)
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#define BE_BRI_RANDSEED (148*4)
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#define BE_BRI_RXCFG (195*4)
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#define BE_BRI_MACADDR2 (198*4)
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#define BE_BRI_MACADDR1 (199*4)
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#define BE_BRI_MACADDR0 (200*4)
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#define BE_BRI_HASHTAB3 (208*4)
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#define BE_BRI_HASHTAB2 (209*4)
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#define BE_BRI_HASHTAB1 (210*4)
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#define BE_BRI_HASHTAB0 (211*4)
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/* be_bregs.xif_cfg: XIF config. */
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#define BE_BR_XCFG_ODENABLE 0x00000001 /* output driver enable */
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#define BE_BR_XCFG_RESV 0x00000002 /* reserved, write as 1 */
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#define BE_BR_XCFG_MLBACK 0x00000004 /* loopback-mode mii enable */
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#define BE_BR_XCFG_SMODE 0x00000008 /* enable serial mode */
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/* be_bregs.stat: status, clear on read. */
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#define BE_BR_STAT_GOTFRAME 0x00000001 /* received a frame */
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#define BE_BR_STAT_RCNTEXP 0x00000002 /* rx frame cntr expired */
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#define BE_BR_STAT_ACNTEXP 0x00000004 /* align-error cntr expired */
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#define BE_BR_STAT_CCNTEXP 0x00000008 /* crc-error cntr expired */
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#define BE_BR_STAT_LCNTEXP 0x00000010 /* length-error cntr expired */
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#define BE_BR_STAT_RFIFOVF 0x00000020 /* rx fifo overflow */
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#define BE_BR_STAT_CVCNTEXP 0x00000040 /* code-violation cntr exprd */
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#define BE_BR_STAT_SENTFRAME 0x00000100 /* transmitted a frame */
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#define BE_BR_STAT_TFIFO_UND 0x00000200 /* tx fifo underrun */
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#define BE_BR_STAT_MAXPKTERR 0x00000400 /* max-packet size error */
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#define BE_BR_STAT_NCNTEXP 0x00000800 /* normal-collision cntr exp */
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#define BE_BR_STAT_ECNTEXP 0x00001000 /* excess-collision cntr exp */
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#define BE_BR_STAT_LCCNTEXP 0x00002000 /* late-collision cntr exp */
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#define BE_BR_STAT_FCNTEXP 0x00004000 /* first-collision cntr exp */
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#define BE_BR_STAT_DTIMEXP 0x00008000 /* defer-timer expired */
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#define BE_BR_STAT_BITS "\177\020" \
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"b\0GOTFRAME\0b\1RCNTEXP\0b\2ACNTEXP\0" \
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"b\3CCNTEXP\0b\5LCNTEXP\0b\6RFIFOVF\0" \
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"b\7CVCNTEXP\0b\10SENTFRAME\0b\11TFIFO_UND\0" \
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"b\12MAXPKTERR\0b\13NCNTEXP\0b\14ECNTEXP\0" \
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"b\15LCCNTEXP\0b\16FCNTEXP\0b\17DTIMEXP\0\0"
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/* be_bregs.imask: interrupt mask. */
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#define BE_BR_IMASK_GOTFRAME 0x00000001 /* received a frame */
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#define BE_BR_IMASK_RCNTEXP 0x00000002 /* rx frame cntr expired */
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#define BE_BR_IMASK_ACNTEXP 0x00000004 /* align-error cntr expired */
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#define BE_BR_IMASK_CCNTEXP 0x00000008 /* crc-error cntr expired */
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#define BE_BR_IMASK_LCNTEXP 0x00000010 /* length-error cntr expired */
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#define BE_BR_IMASK_RFIFOVF 0x00000020 /* rx fifo overflow */
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#define BE_BR_IMASK_CVCNTEXP 0x00000040 /* code-violation cntr exprd */
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#define BE_BR_IMASK_SENTFRAME 0x00000100 /* transmitted a frame */
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#define BE_BR_IMASK_TFIFO_UND 0x00000200 /* tx fifo underrun */
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#define BE_BR_IMASK_MAXPKTERR 0x00000400 /* max-packet size error */
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#define BE_BR_IMASK_NCNTEXP 0x00000800 /* normal-collision cntr exp */
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#define BE_BR_IMASK_ECNTEXP 0x00001000 /* excess-collision cntr exp */
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#define BE_BR_IMASK_LCCNTEXP 0x00002000 /* late-collision cntr exp */
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#define BE_BR_IMASK_FCNTEXP 0x00004000 /* first-collision cntr exp */
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#define BE_BR_IMASK_DTIMEXP 0x00008000 /* defer-timer expired */
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/* be_bregs.tx_cfg: tx config. */
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#define BE_BR_TXCFG_ENABLE 0x00000001 /* enable the transmitter */
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#define BE_BR_TXCFG_FIFO 0x00000010 /* default tx fthresh */
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#define BE_BR_TXCFG_SMODE 0x00000020 /* enable slow transmit mode */
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#define BE_BR_TXCFG_CIGN 0x00000040 /* ignore tx collisions */
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#define BE_BR_TXCFG_FCSOFF 0x00000080 /* do not emit fcs */
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#define BE_BR_TXCFG_DBACKOFF 0x00000100 /* disable backoff */
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#define BE_BR_TXCFG_FULLDPLX 0x00000200 /* enable full-duplex */
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/* be_bregs.rx_cfg: rx config. */
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#define BE_BR_RXCFG_ENABLE 0x00000001 /* enable the receiver */
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#define BE_BR_RXCFG_FIFO 0x0000000e /* default rx fthresh */
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#define BE_BR_RXCFG_PSTRIP 0x00000020 /* pad byte strip enable */
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#define BE_BR_RXCFG_PMISC 0x00000040 /* enable promiscous mode */
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#define BE_BR_RXCFG_DERR 0x00000080 /* disable error checking */
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#define BE_BR_RXCFG_DCRCS 0x00000100 /* disable crc stripping */
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#define BE_BR_RXCFG_ME 0x00000200 /* receive packets for me */
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#define BE_BR_RXCFG_PGRP 0x00000400 /* enable promisc group mode */
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#define BE_BR_RXCFG_HENABLE 0x00000800 /* enable hash filter */
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#define BE_BR_RXCFG_AENABLE 0x00001000 /* enable address filter */
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/*
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* BE Channel registers
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*-
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struct be_cregs {
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u_int32_t ctrl; // control
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u_int32_t stat; // status
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u_int32_t rxds; // rx descriptor ring ptr
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u_int32_t txds; // tx descriptor ring ptr
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u_int32_t rimask; // rx interrupt mask
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u_int32_t timask; // tx interrupt mask
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u_int32_t qmask; // qec error interrupt mask
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u_int32_t bmask; // be error interrupt mask
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u_int32_t rxwbufptr; // local memory rx write ptr
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u_int32_t rxrbufptr; // local memory rx read ptr
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u_int32_t txwbufptr; // local memory tx write ptr
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u_int32_t txrbufptr; // local memory tx read ptr
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u_int32_t ccnt; // collision counter
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};
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* register indices: */
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#define BE_CRI_CTRL (0*4)
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#define BE_CRI_STAT (1*4)
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#define BE_CRI_RXDS (2*4)
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#define BE_CRI_TXDS (3*4)
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#define BE_CRI_RIMASK (4*4)
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#define BE_CRI_TIMASK (5*4)
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#define BE_CRI_QMASK (6*4)
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#define BE_CRI_BMASK (7*4)
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#define BE_CRI_RXWBUF (8*4)
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#define BE_CRI_RXRBUF (9*4)
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#define BE_CRI_TXWBUF (10*4)
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#define BE_CRI_TXRBUF (11*4)
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#define BE_CRI_CCNT (12*4)
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/* be_cregs.ctrl: control. */
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#define BE_CR_CTRL_TWAKEUP 0x00000001 /* tx dma wakeup */
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/* be_cregs.stat: status. */
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#define BE_CR_STAT_BERROR 0x80000000 /* be error */
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#define BE_CR_STAT_TXIRQ 0x00200000 /* tx interrupt */
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#define BE_CR_STAT_TXDERR 0x00080000 /* tx descriptor is bad */
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#define BE_CR_STAT_TXLERR 0x00040000 /* tx late error */
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#define BE_CR_STAT_TXPERR 0x00020000 /* tx parity error */
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#define BE_CR_STAT_TXSERR 0x00010000 /* tx sbus error ack */
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#define BE_CR_STAT_RXIRQ 0x00000020 /* rx interrupt */
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#define BE_CR_STAT_RXDROP 0x00000010 /* rx packet dropped */
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#define BE_CR_STAT_RXSMALL 0x00000008 /* rx buffer too small */
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#define BE_CR_STAT_RXLERR 0x00000004 /* rx late error */
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#define BE_CR_STAT_RXPERR 0x00000002 /* rx parity error */
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#define BE_CR_STAT_RXSERR 0x00000001 /* rx sbus error ack */
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/* be_cregs.qmask: qec error interrupt mask. */
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#define BE_CR_QMASK_TXDERR 0x00080000 /* tx descriptor is bad */
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#define BE_CR_QMASK_TXLERR 0x00040000 /* tx late error */
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#define BE_CR_QMASK_TXPERR 0x00020000 /* tx parity error */
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#define BE_CR_QMASK_TXSERR 0x00010000 /* tx sbus error ack */
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#define BE_CR_QMASK_RXDROP 0x00000010 /* rx packet dropped */
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#define BE_CR_QMASK_RXSMALL 0x00000008 /* rx buffer too small */
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#define BE_CR_QMASK_RXLERR 0x00000004 /* rx late error */
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#define BE_CR_QMASK_RXPERR 0x00000002 /* rx parity error */
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#define BE_CR_QMASK_RXSERR 0x00000001 /* rx sbus error ack */
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/*
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* BE Transceiver registers
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*-
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struct be_tregs {
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u_int32_t tcvr_pal; // transceiver pal
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u_int32_t mgmt_pal; // management pal
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};
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* register indices: */
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#define BE_TRI_TCVRPAL 0
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#define BE_TRI_MGMTPAL 4
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/* be_tregs.tcvr_pal: transceiver pal */
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#define TCVR_PAL_SERIAL 0x00000001 /* serial mode enable */
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#define TCVR_PAL_EXTLBACK 0x00000002 /* external loopback */
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#define TCVR_PAL_MSENSE 0x00000004 /* media sense */
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#define TCVR_PAL_LTENABLE 0x00000008 /* link test enable */
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#define TCVR_PAL_LTSTATUS 0x00000010 /* link test status: p1 only */
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#define TCVR_PAL_BITS "\177\020" \
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"b\0SERIAL\0b\1EXTLBACK\0b\2MSENSE\0" \
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"b\3LTENABLE\0\b4LTSTATUS\0\0"
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/* be_tregs.mgmt_pal: management pal */
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#define MGMT_PAL_DCLOCK 0x00000001 /* data clock strobe */
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#define MGMT_PAL_OENAB 0x00000002 /* output enable */
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#define MGMT_PAL_MDIO 0x00000004 /* MDIO data/attached */
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#define MGMT_PAL_EXT_MDIO MGMT_PAL_MDIO /* external mdio */
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#define MGMT_PAL_EXT_MDIO_SHIFT 2 /* position of ext mdio bit */
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#define MGMT_PAL_TIMEO 0x00000008 /* tx enable timeout error */
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#define MGMT_PAL_INT_MDIO MGMT_PAL_TIMEO /* internal mdio */
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#define MGMT_PAL_INT_MDIO_SHIFT 3 /* position of int mdio bit */
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#define MGMT_PAL_BITS "\177\020" \
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"b\0DLCLOCK\0b\1OENAB\0b\2EXT_MDIO\0" \
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"b\3INT_MDIO\0\0"
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/* Packet buffer size */
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#define BE_PKT_BUF_SZ 2048
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#define MC_POLY_BE 0x04c11db7UL /* mcast crc, big endian */
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#define MC_POLY_LE 0xedb88320UL /* mcast crc, little endian */
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/* PHY addresses */
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#define BE_PHY_EXTERNAL 0
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#define BE_PHY_INTERNAL 1
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