209 lines
6.3 KiB
C
209 lines
6.3 KiB
C
/* $NetBSD: agpreg.h,v 1.7 2004/02/04 06:58:24 soren Exp $ */
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/*-
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* Copyright (c) 2000 Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD: src/sys/pci/agpreg.h,v 1.3 2000/07/12 10:13:04 dfr Exp $
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*/
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#ifndef _PCI_AGPREG_H_
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#define _PCI_AGPREG_H_
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/*
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* Offsets for various AGP configuration registers.
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*/
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#define AGP_APBASE 0x10
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#define AGP_STATUS 0x4
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#define AGP_COMMAND 0x8
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/*
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* Config registers for Intel AGP chipsets.
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*/
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/* i845/855PM */
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#define AGP_I845_AGPMISC 0x51
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# define AGPMISC_AAGN (1U << 1) /* Aperture AccessEN */
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/* i840/850/850E */
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#define AGP_I840_MCHCFG 0x50
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# define MCHCFG_AAGN (1U << 9) /* Aperture AccessEN */
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/* i82443LX/BX/GX */
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#define AGP_INTEL_NBXCFG 0x50
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# define NBXCFG_APAE (1U << 10) /* AGPtoPCI AccessDIS */
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# define NBXCFG_AAGN (1U << 9) /* Aperture AccessEN */
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/* Error Status for i8XX Chipset */
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#define AGP_INTEL_I8XX_ERRSTS 0xc8
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/* Common register */
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#define AGP_INTEL_ERRSTS 0x91 /* Not i8XX */
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#define AGP_INTEL_AGPCMD 0xa8
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# define AGPCMD_SBA (1U << 9)
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# define AGPCMD_AGPEN (1U << 8)
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# define AGPCMD_FWEN (1U << 4)
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# define AGPCMD_RATE_1X (1U << 1)
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# define AGPCMD_RATE_2X (1U << 2)
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# define AGPCMD_RATE_4X (1U << 3)
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#define AGP_INTEL_AGPCTRL 0xb0
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# define AGPCTRL_AGPRSE (1U << 13) /* AGPRSE (82443 only)*/
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# define AGPCTRL_GTLB (1U << 7) /* GTLB EN */
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#define AGP_INTEL_APSIZE 0xb4
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# define APSIZE_MASK 0x3f
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#define AGP_INTEL_ATTBASE 0xb8
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/*
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* Config offsets for VIA AGP chipsets.
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*/
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#define AGP_VIA_GARTCTRL 0x80
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#define AGP_VIA_APSIZE 0x84
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#define AGP_VIA_ATTBASE 0x88
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/*
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* Config offsets for SiS AGP chipsets.
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*/
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#define AGP_SIS_ATTBASE 0x90
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#define AGP_SIS_WINCTRL 0x94
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#define AGP_SIS_TLBCTRL 0x97
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#define AGP_SIS_TLBFLUSH 0x98
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/*
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* Config offsets for Ali AGP chipsets.
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*/
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#define AGP_ALI_AGPCTRL 0xb8
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#define AGP_ALI_ATTBASE 0xbc
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#define AGP_ALI_TLBCTRL 0xc0
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/*
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* Config offsets for the AMD 751 chipset.
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*/
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#define AGP_AMD751_REGISTERS 0x14
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#define AGP_AMD751_APCTRL 0xac
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#define AGP_AMD751_MODECTRL 0xb0
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#define AGP_AMD751_MODECTRL_SYNEN 0x80
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#define AGP_AMD751_MODECTRL2 0xb2
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#define AGP_AMD751_MODECTRL2_G1LM 0x01
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#define AGP_AMD751_MODECTRL2_GPDCE 0x02
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#define AGP_AMD751_MODECTRL2_NGSE 0x08
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/*
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* Memory mapped register offsets for AMD 751 chipset.
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*/
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#define AGP_AMD751_CAPS 0x00
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#define AGP_AMD751_CAPS_EHI 0x0800
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#define AGP_AMD751_CAPS_P2P 0x0400
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#define AGP_AMD751_CAPS_MPC 0x0200
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#define AGP_AMD751_CAPS_VBE 0x0100
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#define AGP_AMD751_CAPS_REV 0x00ff
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#define AGP_AMD751_STATUS 0x02
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#define AGP_AMD751_STATUS_P2PS 0x0800
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#define AGP_AMD751_STATUS_GCS 0x0400
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#define AGP_AMD751_STATUS_MPS 0x0200
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#define AGP_AMD751_STATUS_VBES 0x0100
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#define AGP_AMD751_STATUS_P2PE 0x0008
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#define AGP_AMD751_STATUS_GCE 0x0004
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#define AGP_AMD751_STATUS_VBEE 0x0001
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#define AGP_AMD751_ATTBASE 0x04
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#define AGP_AMD751_TLBCTRL 0x0c
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/*
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* Config registers for i810 device 0
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*/
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#define AGP_I810_SMRAM 0x70
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#define AGP_I810_SMRAM_GMS 0xc0
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#define AGP_I810_SMRAM_GMS_DISABLED 0x00
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#define AGP_I810_SMRAM_GMS_ENABLED_0 0x40
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#define AGP_I810_SMRAM_GMS_ENABLED_512 0x80
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#define AGP_I810_SMRAM_GMS_ENABLED_1024 0xc0
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#define AGP_I810_MISCC 0x72
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#define AGP_I810_MISCC_WINSIZE 0x0001
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#define AGP_I810_MISCC_WINSIZE_64 0x0000
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#define AGP_I810_MISCC_WINSIZE_32 0x0001
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#define AGP_I810_MISCC_PLCK 0x0008
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#define AGP_I810_MISCC_PLCK_UNLOCKED 0x0000
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#define AGP_I810_MISCC_PLCK_LOCKED 0x0008
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#define AGP_I810_MISCC_WPTC 0x0030
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#define AGP_I810_MISCC_WPTC_NOLIMIT 0x0000
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#define AGP_I810_MISCC_WPTC_62 0x0010
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#define AGP_I810_MISCC_WPTC_50 0x0020
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#define AGP_I810_MISCC_WPTC_37 0x0030
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#define AGP_I810_MISCC_RPTC 0x00c0
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#define AGP_I810_MISCC_RPTC_NOLIMIT 0x0000
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#define AGP_I810_MISCC_RPTC_62 0x0040
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#define AGP_I810_MISCC_RPTC_50 0x0080
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#define AGP_I810_MISCC_RPTC_37 0x00c0
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/*
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* Config registers for i810 device 1
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*/
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#define AGP_I810_GMADR 0x10
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#define AGP_I810_MMADR 0x14
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/*
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* Memory mapped register offsets for i810 chipset.
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*/
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#define AGP_I810_PGTBL_CTL 0x2020
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#define AGP_I810_DRT 0x3000
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#define AGP_I810_DRT_UNPOPULATED 0x00
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#define AGP_I810_DRT_POPULATED 0x01
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#define AGP_I810_GTT 0x10000
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/*
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* Config registers for i830MG device 0
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*/
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#define AGP_I830_GCC0 0x50
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#define AGP_I830_GCC1 0x52
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#define AGP_I830_GCC1_DEV2 0x08
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#define AGP_I830_GCC1_DEV2_ENABLED 0x00
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#define AGP_I830_GCC1_DEV2_DISABLED 0x08
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#define AGP_I830_GCC1_GMS 0x70
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#define AGP_I830_GCC1_GMS_STOLEN_512 0x20
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#define AGP_I830_GCC1_GMS_STOLEN_1024 0x30
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#define AGP_I830_GCC1_GMS_STOLEN_8192 0x40
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#define AGP_I830_GCC1_GMASIZE 0x01
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#define AGP_I830_GCC1_GMASIZE_64 0x01
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#define AGP_I830_GCC1_GMASIZE_128 0x00
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/*
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* Config registers for 852GM/855GM/865G device 0
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*/
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#define AGP_I855_GCC1 0x52
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#define AGP_I855_GCC1_DEV2 0x08
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#define AGP_I855_GCC1_DEV2_ENABLED 0x00
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#define AGP_I855_GCC1_DEV2_DISABLED 0x08
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#define AGP_I855_GCC1_GMS 0x70
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#define AGP_I855_GCC1_GMS_STOLEN_0M 0x00
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#define AGP_I855_GCC1_GMS_STOLEN_1M 0x10
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#define AGP_I855_GCC1_GMS_STOLEN_4M 0x20
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#define AGP_I855_GCC1_GMS_STOLEN_8M 0x30
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#define AGP_I855_GCC1_GMS_STOLEN_16M 0x40
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#define AGP_I855_GCC1_GMS_STOLEN_32M 0x50
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#endif /* !_PCI_AGPREG_H_ */
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