262 lines
7.5 KiB
C
262 lines
7.5 KiB
C
/* $NetBSD: iq80310_pci.c,v 1.8 2003/07/15 00:25:03 lukem Exp $ */
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/*
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* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* IQ80310 PCI interrupt support, using he i80312 Companion I/O chip.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: iq80310_pci.c,v 1.8 2003/07/15 00:25:03 lukem Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <machine/autoconf.h>
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#include <machine/bus.h>
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#include <evbarm/iq80310/iq80310reg.h>
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#include <evbarm/iq80310/iq80310var.h>
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#include <arm/xscale/i80312reg.h>
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#include <arm/xscale/i80312var.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/ppbreg.h>
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int iq80310_pci_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
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const char *iq80310_pci_intr_string(void *, pci_intr_handle_t);
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const struct evcnt *iq80310_pci_intr_evcnt(void *, pci_intr_handle_t);
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void *iq80310_pci_intr_establish(void *, pci_intr_handle_t,
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int, int (*func)(void *), void *);
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void iq80310_pci_intr_disestablish(void *, void *);
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void
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iq80310_pci_init(pci_chipset_tag_t pc, void *cookie)
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{
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pc->pc_intr_v = cookie; /* the i80312 softc */
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pc->pc_intr_map = iq80310_pci_intr_map;
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pc->pc_intr_string = iq80310_pci_intr_string;
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pc->pc_intr_evcnt = iq80310_pci_intr_evcnt;
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pc->pc_intr_establish = iq80310_pci_intr_establish;
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pc->pc_intr_disestablish = iq80310_pci_intr_disestablish;
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}
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#if defined(IOP310_TEAMASA_NPWR)
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int
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iq80310_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
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{
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struct i80312_softc *sc = pa->pa_pc->pc_intr_v;
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pcireg_t reg;
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int sbus;
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/*
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* The Npwr routes #INTA of the on-board PCI devices directly
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* through the CPLD. There is no PCI-PCI bridge and no PCI
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* slots on the Npwr.
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*
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* We also expect the devices to be on the Secondary side of
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* the i80312.
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*/
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reg = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO);
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sbus = PPB_BUSINFO_SECONDARY(reg);
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if (pa->pa_bus != sbus) {
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printf("iq80310_pci_intr_map: %d/%d/%d not on Secondary bus\n",
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pa->pa_bus, pa->pa_device, pa->pa_function);
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return (1);
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}
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switch (pa->pa_device) {
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case 5: /* LSI 53c1010 SCSI */
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*ihp = XINT3_IRQ(2);
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break;
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case 6: /* Intel i82544GC Gig-E #1 */
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*ihp = XINT3_IRQ(1);
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break;
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case 7: /* Intel i82544GC Gig-E #2 */
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*ihp = XINT3_IRQ(4);
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break;
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default:
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printf("iq80310_pci_intr_map: no mapping for %d/%d/%d\n",
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pa->pa_bus, pa->pa_device, pa->pa_function);
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return (1);
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}
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return (0);
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}
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#else /* Default to stock IQ80310 */
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int
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iq80310_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
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{
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struct i80312_softc *sc = pa->pa_pc->pc_intr_v;
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pcitag_t tag;
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pcireg_t reg;
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int sbus, pbus;
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/*
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* Mapping of PCI interrupts on the IQ80310 is pretty easy; there
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* is a single interrupt line for all PCI devices on pre-F boards,
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* and an interrupt line for each INTx# signal on F and later boards.
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*
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* The only exception is the on-board Ethernet; this devices has
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* its own dedicated interrupt line. The location of this device
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* looks like this:
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*
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* 80312 Secondary -> PPB at dev #7 -> i82559 at dev #0
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*
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* In order to determine if we're mapping the interrupt for the
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* on-board Ethernet, we must read the Secondary Bus # of the
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* i80312, then use that to read the Secondary Bus # of the
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* 21154 PPB. At that point, we know that b/d/f of the i82559,
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* and can determine if we're looking at that device.
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*/
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reg = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO);
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pbus = PPB_BUSINFO_PRIMARY(reg);
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sbus = PPB_BUSINFO_SECONDARY(reg);
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/*
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* XXX We don't know how to map interrupts on the Primary
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* XXX PCI bus right now.
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*/
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if (pa->pa_bus == pbus) {
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printf("iq80310_pci_intr_map: can't map interrupts on "
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"Primary bus\n");
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return (1);
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}
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tag = pci_make_tag(pa->pa_pc, sbus, 7, 0);
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/* Make sure the PPB is there. */
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reg = pci_conf_read(pa->pa_pc, tag, PCI_ID_REG);
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if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID ||
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PCI_VENDOR(reg) == 0) {
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/*
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* That's odd... no PPB there? Oh well, issue a warning
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* and continue on.
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*/
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printf("iq80310_pci_intr_map: PPB not found at %d/%d/%d ??\n",
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sbus, 7, 0);
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goto pinmap;
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}
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/* Make sure the device that's there is a PPB. */
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reg = pci_conf_read(pa->pa_pc, tag, PCI_CLASS_REG);
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if (PCI_CLASS(reg) != PCI_CLASS_BRIDGE ||
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PCI_SUBCLASS(reg) != PCI_SUBCLASS_BRIDGE_PCI) {
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/*
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* That's odd... the device that's there isn't a PPB.
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* Oh well, issue a warning and continue on.
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*/
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printf("iq80310_pci_intr_map: %d/%d/%d isn't a PPB ??\n",
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sbus, 7, 0);
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goto pinmap;
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}
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/* Now read the PPB's secondary bus number. */
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reg = pci_conf_read(pa->pa_pc, tag, PPB_REG_BUSINFO);
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sbus = PPB_BUSINFO_SECONDARY(reg);
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if (pa->pa_bus == sbus && pa->pa_device == 0 &&
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pa->pa_function == 0) {
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/* On-board i82559 Ethernet! */
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*ihp = XINT3_IRQ(XINT3_ETHERNET);
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return (0);
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}
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pinmap:
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if (pa->pa_intrpin == 0) {
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/* No IRQ used. */
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return (1);
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}
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if (pa->pa_intrpin > 4) {
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printf("iq80310_pci_intr_map: bad interrupt pin %d\n",
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pa->pa_intrpin);
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return (1);
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}
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/* INTD# is always in XINT3. */
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if (pa->pa_intrpin == 4) {
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*ihp = XINT3_IRQ(XINT3_SINTD);
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return (0);
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}
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/* On pre-F boards, ALL of them are on XINT3. */
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if (/*pre-F*/0)
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*ihp = XINT3_IRQ(XINT3_SINTD);
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else
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*ihp = XINT0_IRQ(pa->pa_intrpin - 1);
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return (0);
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}
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#endif /* list of IQ80310-based designs */
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const char *
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iq80310_pci_intr_string(void *v, pci_intr_handle_t ih)
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{
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static char irqstr[IRQNAMESIZE];
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sprintf(irqstr, "iq80310 irq %ld", ih);
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return (irqstr);
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}
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const struct evcnt *
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iq80310_pci_intr_evcnt(void *v, pci_intr_handle_t ih)
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{
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/* XXX For now. */
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return (NULL);
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}
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void *
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iq80310_pci_intr_establish(void *v, pci_intr_handle_t ih, int ipl,
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int (*func)(void *), void *arg)
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{
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return (iq80310_intr_establish(ih, ipl, func, arg));
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}
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void
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iq80310_pci_intr_disestablish(void *v, void *cookie)
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{
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iq80310_intr_disestablish(cookie);
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}
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